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Volumn , Issue , 2005, Pages 217-235

XHDL: Extending VHDL to improve core parameterization and reuse

Author keywords

component based design; HDL; IP; parameterization; reuse

Indexed keywords


EID: 84885707167     PISSN: None     EISSN: None     Source Type: Book    
DOI: 10.1007/0-387-26151-6_16     Document Type: Chapter
Times cited : (2)

References (13)
  • 2
    • 84885697425 scopus 로고    scopus 로고
    • Confluence (2004). Confluence language. http://www.confluent.org.
    • (2004) Confluence Language
  • 3
    • 0008925849 scopus 로고    scopus 로고
    • Reuse and protection of intellectual property in the SpecC system
    • Dömer, R. and Gajski, D. (2000). Reuse and Protection of Intellectual Property in the SpecC System. In Proc. ASP-DAC.
    • (2000) Proc. ASP-DAC
    • Dömer, R.1    Gajski, D.2
  • 6
    • 84885735889 scopus 로고    scopus 로고
    • A web-based environment for the evaluation and generation of complex IP cores
    • Fernández, A., Sánchez, M. A., and López-Vallejo, M. (2004). A Web-based Environment for the Evaluation and Generation of Complex IP Cores. In IP-SOC.
    • (2004) IP-SOC
    • Fernández, A.1    Sánchez, M.A.2    López-Vallejo, M.3
  • 8
    • 0034795611 scopus 로고    scopus 로고
    • SystemC-A modeling platform supporting multiple design abstractions
    • Panda, P. R. (2001). SystemC-A Modeling Platform Supporting Multiple Design Abstractions. In 14th Intl. Symposium on System Synthesis.
    • (2001) 14th Intl. Symposium on System Synthesis
    • Panda, P.R.1
  • 11
    • 84885707432 scopus 로고    scopus 로고
    • Scalable parallel architecture for ultra fast FFT in an FPGA
    • Rémondeau, J.-M. (1999). Scalable parallel architecture for ultra fast FFT in an FPGA. In Proc. ICSPAT.
    • (1999) Proc. ICSPAT
    • Rémondeau, J.-M.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.