Statistical power estimation for FPGA'S

Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL

Volumn 2005, Issue , 2005, Pages 515-518

  Todorovich, Elias ^a   Boemo, Eduardo ^a   Angarita, Fabian ^b   Valls, Javier ^b  

^a UNIVERSIDAD AUTÓNOMA DE MADRID   (Spain)

^b UNIVERSITAT POLITÈCNICA DE VALÈNCIA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

BLOCK CODES; COMPUTER AIDED DESIGN; DIGITAL FILTERS; ERROR ANALYSIS; OPTIMIZATION; STATISTICAL METHODS;

DESIGN FLOW; POWER MAPS GENERATION; POWER OPTIMIZATION; SHORT PULSE FILTRATION;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 33746921263     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2005.1515774     Document Type: Conference Paper

References (16)

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