Optimal set of body bias voltages for an FPGA with field-programmable vth components

Proceedings - 2006 IEEE International Conference on Field Programmable Technology, FPT 2006

Volumn , Issue , 2006, Pages 329-332

  Kawanami, Takashi ^a   Hioki, Masakazu ^a   Matsumoto, Yohei ^a   Tsutsumi, Toshiyuki ^a,b   Nakagawa, Tadashi ^a   Sekigawa, Toshihiro ^a   Koike, Hanpei ^a  

^a NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY AIST   (Japan)

^b MEIJI UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BIAS VOLTAGE; ELECTRIC POWER UTILIZATION; OPTIMIZATION; ROUTING PROTOCOLS; STATIC ANALYSIS; THRESHOLD VOLTAGE; TRANSISTORS;

CIRCUIT BLOCKS; PERFORMANCE DEGRADATION; POWER REDUCTION;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 43749102061     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPT.2006.270340     Document Type: Conference Paper

References (21)

1. S. Borkar, "Low power design challenges for the decade," ASP-DAC pp.293-296, 2001.
2. D. Deleganes, J. Douglas, B. Kommandur and M. Patyra, "Designing a 3GHz, 130nm, Pentium. 4 processor," Symp. on VLSI Circuits, pp.130-133, 2002.
3. J. Clabes, J. Friedrich, M. Sweet, J. DiLullo, S. Chu, D. Plass, J. Dawson, P. Muench, L. Powell, M. Floyd, B. Sinharoy, M. Lee, M. Goulet, J. Wagoner, N. Schwartz, S. Runyon, G. Gorman, P. Resile, R. Kalla, J. McGill and S. Dodson, "Design and implementation of the POWER5™ microprocessor," ISSCC, pp.56-57, 2004.
4. T. Kuroda, T. Fujita, S. Mita, T. Nagamatu, S. Yoshioka, F. Sano, M. Norishima, M. Murota, M. Kako, M. Kinugawa, M. Kakumu, and T. Sakurai, "A 0.9V 150MHz 10mW 4mm 2-D discrete cosine transform core processor with variable-threshold-voltage scheme," ISSCC, pp.166-167, Feb. 1996.
5. T. Sekigawa and Y. Hayashi, "Calculated Threshold-Voltage Characteristics of an XMOS Transistor Having an Additional Bottom Gate," Solid State Electron, vol.27, pp.827-828, 1984.
6. F. Li, Yl Lin, L. He, J. Cong, "Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics," ISFPGA, pp.42-50, 2004.
7. http://www.xilinx.com/
8. A. Rahman and V. Polavarapuv "Evaluation of low-leakage design techniques for field programmable gate arrays," ISFPGA, pp.23-30, 2004.
9. A. Rahman, S. Das, T. Tuan, A. Rahut, "Heterogeneous Routing Architecture for Low-Power FPGA Fabric," CICC, pp.183-186, 2005.
10. A. Gayasen, Y. Tsai, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, T. Tuan,"Reducing leakage energy in FPGAs using region-constrained placement," ISFPGA, pp.51-58, 2004.
11. J. H. Anderson, F. N. Najm, "Low-Power Programmable Routing Circuitry for FPGAs," ICCAD, pp.602-609, 2004.
12. Y. Lin, F. Li, L. He, "Routing Track Duplication, with Fine-Grained Power-Gating for FPGA Interconnect Power Reduction", ASP-DAC, pp.645-650, 2005.
13. C. Q. Tran, H. Kawaguchi, T. Sakurai, "95% Leakage-Reduced FPGA using Zigzag Power-gating Dual-Vth/VDD and Micro-VDD-Hopping," A-SSCC, pp.149-152, 2005.
14. T. Tuan, S. Kao, A. Rahman, S. Das and S. Trimberger, "A 90nm Low-Power FPGA for Battery-Powered Applications," ISFPGA, pp.3-11, 2006.
15. T. Kawanami, M. Hioki, H. Nagase, T. Tsutsumi, T. Nakagawa, T. Sekigawa and H. Koike, "Preliminary Evaluation of Flex Power FPGA: A Power Reconfigurable Architecture with Fine Granularity," IEICE Trans. on Inf. & Syst., vol.E87-D, no.8, pp.2004-2010, 2004.
16. M. Hioki, T. Kawanami, T. Tsutsumi, T. Nakagawa, T. Sekigawa and H. Koike, "Can A Cool Chip Be Hot? Yes, Flex Power FPGA Can," COOL Chips VII, vol.1, pp.49-57, 2004.
17. V. Betz and J. Rose, "VPR: A New Packing, Placement and Routing Tool for FPGA Research," FPL, pp.213-222, 1997.
18. Y. Cao, T. Sato, D. Sylvester, M. Orshansky, and C. Hu, "New paradigm of predictive MOSFET and interconnect modeling for early circuit design," CICC, pp. 201-204, June 2000.
19. S. Yang, "Logic Synthesis and Optimization Benchmarks, Version 3.0," Tech. Report, Microelectronics Centre of North Carolina, 1991.
20. V. Betz, J. Rose, and A. Marquardt, "Architecture and CAD for Deep-Submicron FPGAs," Kluwer Academic Publishers, Norwell, MA, 1999.
21. Y. Yasuda, N. Kimizuka, Y. Akiyama, Y. Yamagata, Y. Goto, K. Imai, "System LSI Multi-Vth Transistors Design Methodology for Maximizing Efficiency of Body-Biasing Control to Reduce Vth Variation and Power Consumption," IEDM, pp.73-76, 2005.