Low power design challenges for the decade

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2001-January, Issue , 2001, Pages 293-296

  Borkar, S ^a  

^a INTEL CORPORATION   (United States)

Author keywords

Circuit synthesis; Clocks; Design automation; Dynamic voltage scaling; Energy consumption; Frequency; Logic; Microarchitecture; Microprocessors; Moore's Law

Indexed keywords

AUTOMATION; CLOCKS; COMPUTATION THEORY; COMPUTER AIDED DESIGN; ELECTRIC POWER SUPPLIES TO APPARATUS; ENERGY UTILIZATION; INTEGRATED CIRCUIT MANUFACTURE; MICROPROCESSOR CHIPS; VOLTAGE SCALING;

CIRCUIT SYNTHESIS; DESIGN AUTOMATIONS; FREQUENCY; LOGIC; MICRO ARCHITECTURES; MOORE'S LAW;

DESIGN;

EID: 84949746044     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2001.913321     Document Type: Conference Paper

References (6)

1. S. Borkar, "Design Challenges of Technology Scaling," IEEE Micro, July/Aug, 1999.
2. Intel SpeedStep™ technology, http://www.intel.com.
3. D. Ditzel, "Transmeta's Crusoe," Proceedings of COOL Chips III conference, Tokyo, Japan, April 24-25, 2000.
4. Y. Ye, S. Borkar, V. De, "A New Technique for Standby Leakage Reduction in High-Performance Circuits," 1998 Symposium on VLSI Circuits, June 1998.
5. A. Chandrakasan, W. Bowhill, F. Fox, "Design of High Performance Microprocessor Circuits," IEEE Press, Chapter 3.
6. F. Pollack, "New Microarchitecture Challenges in the Coming Generations of CMOS Process Technologies", Micro32, 1999.