Flexible reconfigurable multiplier blocks suitable for enhancing the architecture of FPGAs

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 1999, Pages 191-194

  Haynes, Simon D ^a   Ferrari, Antonio B ^a   Cheung, Peter Y K ^a  

^a IMPERIAL COLLEGE LONDON   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; DIGITAL ARITHMETIC; FIELD PROGRAMMABLE GATE ARRAYS; THREE DIMENSIONAL COMPUTER GRAPHICS;

BINARY MULTIPLICATION; FLEXIBLE RECONFIGURABLE BLOCKS; MULTIPLY ACCUMULATE;

MULTIPLYING CIRCUITS;

EID: 0032597867     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (10)