A maximum total leakage current estimation method

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 2, Issue , 2004, Pages

  Xu, Yongjun ^a   Luo, Zuying ^b   Li, Xiaowei ^a  

^a INSTITUTE OF COMPUTING TECHNOLOGY   (China)

^b TSINGHUA UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; CONSTRAINT THEORY; ERROR ANALYSIS; ESTIMATION; INTEGRATED CIRCUIT LAYOUT; SEMICONDUCTOR JUNCTIONS;

INTEGRATED CIRCUIT DESIGN; LEAKAGE CURRENT ESTIMATION; LEAKAGE CURRENT SIMULATORS; OPERATING TEMPERATURE;

LEAKAGE CURRENTS;

EID: 4344715582     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (22)

1. Kaushik Roy, Sharat Prasad. "Low Power CMOS VLSI Circuit Design [M]", New York: A Wiley Interscience Publication, 2000.
2. Jams Kao, Siva Narendra and Anantha Chandrakasan, "Subthreshold Leakage Modeling and Reduction Techniques", In Proceeding of ICCAD, San Jose, CA, pp28-34, Nov. 10-14, 2002.
3. Saibal Mukhopadhyay, Arijit Raychowdhury, and Kaushik Roy, "Accurate Estimation of Total Leakage Current in Scaled CMOS Logic Circuits Based on Compact Current Modeling", DAC'03, Anaheim, California, USA, pp169-174, June 2-6, 2003.
4. Z. Chen, et.al., "Estimation of Standby leakage Power in CMOS Circuits Considering Accurate Modeling of Transistor Stacks". ISLPED'98, pp239-244, 1998.
5. S. Bobba, I. N. Hajj, "Maximum Leakage Power Estimation for CMOS Circuits", Proceedings of IEEE VOLTA99, Como, Italy, pp116-124, March 4-5, 1999.
6. W. Shiue, "Leakage Power Estimation and Minimization in VLSI Circuits", ISCAS'01, 2001, pp.l78-181.
7. Vivek De, "Leakage-tolerant design techniques for high performance processors (Invited paper)"[J], Proceedings of 2002 International Symposium on Physical Design, San Diego, California, USA, P28, April 7-10, 2002.
8. Koushik K Das, Richard B Brown, "Ultra Low -Leakage Power Strategies for Sub-1 V VLSI: Novel Circuit Styles and Design Methodologies for Partially Depleted Silicon-On-Insulator (SOI) CMOS Technology", Proceedings of the 16th International Conference on VLSI Design (VLSI 03), New Delhi, India, pp291-296, 2003.
9. C.-H. Choi, et al., "Impact of Gate Direct Tunneling on Circuit performance: a Simulation Study", IEEE Tran. on Electron Devices, Dec. pp2823-2829, 2001.
10. S. Schwantes and W. Krautschneider, "Relevance of Gate Current for the Functionality of Deep Submicron CMOS Circuits", European Solid-State Device Research Conf., 2001.
11. Dongwoo Lee, Wesley Kwong, David Blaauw, and et al. "Simultaneous Subthreshold and Gate-Oxide Tunneling Leakage Current Analysis in Nanometer CMOS design", in 4th International Symposium on Quality Electronic Design (ISQED), pp287-292, 2003.
12. Dongwoo Lee, Wesley Kwong, David Blaauw, and et al. "Analysis and Minimization Techniques for Total Leakage Considering Gate Oxide Leakage", DAC'03, Anaheim, California, USA, pp175-180, June 2-6, 2003.
13. Saibal Mukhopadhyay, Kaushik Roy, "Modeling and Estimation of Total Leakage Current in Nano-scaled CMOS Devices Considering the Effect of Parameter Variation", ISLPED'03, Seoul, Korea, pp172-175, August 25-27, 2003.
14. R. X. Gu and M. I. Elmasry, "Power Dissipation Analysis and Optimization of Deep Submicron CMOS Digital Circuits"[J], IEEE Journal on Solid State Circuits, vol. 31, No. 5, pp887-893, May 1996.
15. S. Bobba and I. N. Hajj, "Maximum Leakage Power Estimation for CMOS Circuits", Proceedings of IEEE VOLTA99, Como, Italy, pp116-124, March 4-5, 1999.
16. M. C. Johnson, D. Somasekhar and K. Roy, "Models and Algorithms for Bounds on Leakage in CMOS Circuits", IEEE Transaction on CAD of Integrated Circuits, vol.18 no.6, pp714-725, June 1999.
17. José Pineda de Gyvez, Eric van de Wetering, "Average Leakage Current Estimation of CMOS Logic Circuits", Proceedings of the 19th IEEE VLSI Test Symposium (VTS'01), Marina Del Rey, CA, pp375-379, March 29 - April 03, 2001.
18. W.Jiang, V.Tiwari, E.lglesia, and et al. "Topological Analysis for Leakage Prediction of Digital Circuits", In Proceeding of 7th ASPDAC and 15th VLSI Design, Bangalore, pp39-44, 2002.
19. B.J.Sheu, et al., "BSIM: Berkeley Short-Channel IGFET Model for MOS Transistors", IEEE Journal of Solid-State Circuits, vol.22, pp558-566, Aug. 1987.
20. Y.Taur, T.H.Ning, "Fundamentals of Modem VLSI Devices", Cambridge University Press, 1998.
21. http://www-device.eecs.berkeley.edu/~ptm/
22. http://www.erc.msstate.edu/mpl/distributions/scmos/