Improved radix-4 and radix-8 FFT algorithms

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 3, Issue , 2004, Pages

  Bouguezel, Saad ^a   Ahmad, M Omair ^a   Swamy, M N S ^a  

^a Gina Cody School of Engineering and Computer Science   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; EVALUATION; INTEGRAL EQUATIONS; MATRIX ALGEBRA; PROBABILITY DENSITY FUNCTION;

COOLEY-TUKEY; DECIMATION-IN-FREQUENCY (DIF); RADIX-4; STRUCTURAL COMPLEXITIES;

FAST FOURIER TRANSFORMS;

EID: 4344690094     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. L. Jia, Y. Gao and H. Tenhumen, "Efficient VLSI implementation of radix-8 FFT algorithm," in Proc. IEEE Pacific Rim Conf., Communications, Computers and Signal Processing, 1999, pp. 468-471.
2. Y. Ma, "An effective memory addressing scheme for FFT processors," IEEE Trans. Signal Processing, vol. 47, pp.907-911, Mar. 1999.
3. Y. Ma and L. Wanhammar, "A hardware efficient control of memory addressing for high-performance FFT processors," IEEE Trans. Signal Processing, vol. 48, pp.917-921, Mar. 2000
4. Y. Jiang, T. Zhou, Y. Tang and Y. Wang, "Twiddle-factor-based FFT algorithm with reduced memory access," in Proc. IEEE IPDPS'2002, April 2002, pp. 70-77.
5. Q. Li, N. Wang, B. Shi and C. Zheng, "Extendible look-up table of twiddle factors and radix-8 based Fourier transform," Signal Processing, vol. 82, pp. 643-648, 2002.
6. M. Hasan and T. Arslan, " A coefficient memory addressing scheme for VLSI implementation of FFT processors," in Proc. IEEE ISCAS'2002, vol. 4, 2002, pp. 850-853.
7. Y. Tang, Y. Jiang and Y. Wang, "Reduce FFT memory reference for low power applications," in Proc. IEEE ICASSP'2002, vol. 3, 2002, pp. 3204-3207.
8. M. Hasan, T. Arslan and J. S. Thompson, "A novel coefficient ordering based low power pipelined radix-4 FFT processor for wireless LAN applications," IEEE Trans. Consumer Electronics, vol. 49, pp. 128-134, Feb. 2003.
9. Y. Tang, L. Qian, Y. Wang and Y. Savaria, "A new memory reference reduction method for FFT implementation on DSP," in Proc. IEEE ICASP'2003, vol. 4, May 2003, pp. 496-499
10. Y. N. Chang and K. K. Parhi, "An efficient pipelined FFT architecture," IEEE Trans. Circuits Systems II, vol. 50, pp. 322-325, June 2003.