An Effective Memory Addressing Scheme for FFT Processors

IEEE Transactions on Signal Processing

Volumn 47, Issue 3, 1999, Pages 907-911

  Ma, Yutai ^a  

^a INSTITUTE OF COMPUTING TECHNOLOGY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

DATA STORAGE EQUIPMENT; FAST FOURIER TRANSFORMS; STORAGE ALLOCATION (COMPUTER);

MEMORY ADDRESSING ASSIGNMENT;

PIPELINE PROCESSING SYSTEMS;

EID: 0033101737     PISSN: 1053587X     EISSN: None     Source Type: Journal    
DOI: 10.1109/78.747802     Document Type: Article

References (5)

1. D. Cohen, "Simplified control of FFT hardware," IEEE Trans. Acoust., Speech, Signal Processing, vol. ASSP-24, pp. 577-579, Dec. 1976.
2. L. G. Johnson, "Conflict free memory addressing for dedicated FFT hardware," IEEE Trans. Circuits Syst. II, vol. 39, pp. 312-316, May 1992.
3. T. F. Ngai, M. J. Irwin, and S. Rawat, "Regular, area-time efficient carry lookahead adders," J. Parallel Distrib. Comput., vol. 3, no. 1, pp. 92-105, Mar. 1986.
4. M. C. Pease, "Organization of large scale fourier processors," J. Assoc. Comput. Mach., vol. 16, pp. 474-482, July 1969.
5. B. P. Sinha, J. Dattagupta, and A. Sen, "A cost effective FFT processor using memory segmentation," in Proc. IEEE ISCAS, 1983, vol. 1, pp. 20-23.