A hardware efficient control of memory addressing for high-performance FFT processors

IEEE Transactions on Signal Processing

Volumn 48, Issue 3, 2000, Pages 917-921

  Ma, Yutai ^a   Wanhammar, Lars ^b  

^a ROYAL INSTITUTE OF TECHNOLOGY   (Sweden)

^b LINKÖPING UNIVERSITY   (Sweden)

Author keywords

Conflict free memory addressing; Fast fourier trasform; Fft coefficient access; Low power fft processors

Indexed keywords

ALGORITHMS; FAST FOURIER TRANSFORMS; LOGIC DESIGN; MICROPROCESSOR CHIPS; ROM;

COHEN BUTTERFLY SEQUENCE; CONFLICT FREE MEMORY ADDRESSING; FAST FOURIER TRANSFORM COEFFICIENT ACCESS; LOW POWER FAST FOURIER TRANSFORM PROCESSORS;

DIGITAL SIGNAL PROCESSING;

EID: 0033904240     PISSN: 1053587X     EISSN: None     Source Type: Journal    
DOI: 10.1109/78.824693     Document Type: Article

References (10)

1. B. M. Baas, "A 9.5 mW 330 (Isec 1024-point FFT processor," in Proc. Custom Integrated Circuits Conf.. May 1998.
2. _, "An energy-efficient single-chip FFT processor," in Proc. IEEE Symp. VLSI Circuits. June 1996.
3. _, "An energy-efficient FFT processor architecture," StarLab Tech. Rep., NGT-70340-1994-1, Jan. 25, 1994.
4. E. Bidet, D. Castelain, C. Joanblanq, and P. Senn, "A fast single-chip implementation of 8192 complex point FFT," IEEE J. Solid-State Circuits, vol. 30, Mar. 1995.
5. D. Cohen, "Simplified control of FFT hardware," IEEE Trans. Acoust., Speech Signal Processing, vol. ASSP-24, pp. 577-579, Dec. 1976.
6. L. G. Johnson, "Conflict free memory addressing for dedicate FFT hardware," IEEE Trans. Circuits Syst. II. vol. 39, pp. 312-316, May 1992.
7. Y. Ma, "An effective memory addressing scheme for FFT processors," IEEE Trans. Signal Processing, vol. 47, pp. 907-911, Mar. 1999.
8. _, "A VLSI oriented parallel FFT algorithm," IEEE Trans. Signal Processing, vol. 44, pp. 445-448, Feb. 1996.
9. M. C. Pease, "Organization of large scale Fourier processors," J. Assoc. Comput. Mach., vol. 16, pp. 474-482, July 1969.
10. L. Wanhammar, DSP Integrated Circuits. New York: Academic, 1999.