Simulated annealing search through general structure floorplans using sequence-pair

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 3, Issue , 2000, Pages III-77-III-80

  Kiyota, Koji ^a   Fujiyoshi, Kunihiro ^a  

^a TOKYO UNIVERSITY OF AGRICULTURE AND TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT LAYOUT; SIMULATED ANNEALING;

SEQUENCE-PAIR METHOD;

VLSI CIRCUITS;

EID: 18544396649     PISSN: 02714310     EISSN: None     Source Type: Journal    
DOI: 10.1109/ISCAS.2000.856000     Document Type: Article

References (6)

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3. H. Murata K. Fujiyoshi T. Watanabe Y. Kajitani A Mapping from Sequence-Pair to Rectangular Dissection ASP-DAC 625 633 1997
4. S. Nakatake K. Fujiyoshi H. Murata Y. Kajitani Module Packing Based on the BSG-Structure and IC Layout Applications IEEE trans. CAD 17 6 519 530 1998
5. S. Nakatake K. Sakanushi Y. Kajitani M. Kawakita The Channeled-BSG: A Universal Floorplan for Simultaneous Place/Route with IC Applications Proc. IEEE ICCAD 418 425 Proc. IEEE ICCAD 1998
6. H. Onodera Y. Taniguchi K. Tamaru Branch-and-bound placement for building block layout Proc. 28th ACM/IEEE DAC 433 439 Proc. 28th ACM/IEEE DAC 1991