Arbitrary convex and concave rectilinear block packing using sequence-pair

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 19, Issue 2, 2000, Pages 224-233

  Fujiyoshi, Kunihiro ^a   Murata, Hiroshi ^b  

^a TOKYO UNIVERSITY OF AGRICULTURE AND TECHNOLOGY   (Japan)

^b MicroArk Company Ltd   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CONSTRAINT THEORY; INTEGRATED CIRCUIT MANUFACTURE; SET THEORY; TOPOLOGY; VLSI CIRCUITS;

CONCAVE RECTILINEAR BLOCK PACKING; CONVEX RECTILINEAR BLOCK PACKING; SEQUENCE PAIR;

INTEGRATED CIRCUIT LAYOUT;

EID: 0033885149     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.828551     Document Type: Article

References (20)

1. [ l ] Y.-Z. Liao and C. K. Wong, "An algorithm to compact a VLSI symbolic layout with mixed constraints," IEEE Trans. Computer-Aided Design, vol. 2, pp. 62-69, Feb. 1983.
2. T. Ohtsuki, M. Sato, M. Tachibana, and S. Torii, "Minimum partitioning of rectilinear regions," Trans. IPSJ, vol. 24, no. 5, pp. 647-653, 1983.
3. T. Yoshimura, "A graph theoretical compaction algorithm," in Proc. ISCAS'85, 1985, pp. 1455-1458.
4. J. A. McHugh, Algorithmic Graph Theory. Englewood Cliffs, NJ: Prentice Hall, 1990.
5. H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani, "Rectangle-packing-based module placement," in Proc. ICCAD'95, 1995, pp. 47279.
6. T. Takahashi, "An algorithm for finding a maximum weight decreasing sequence in a permutation, motivated by rectangle packing problem," Tech. Rep. IEICE, vol. VLD96, no. 201, pp. 31-35, 1996.
7. S. Nakatake, K. Fujiyoshi, H. Murata, and Y Kajitani, "Module placement on BSG structure and VLSI layout applications," in Proc. ICC AD'96, 1996, pp. 484-491.
8. H. Murata, K. Fujiyoshi, S. Nakatake, and Y Kajitani, "VLSI module placement based on rectangle-packing by the sequence-pair," IEEE Trans. Computer-Aided Design, vol. 15, pp. 1518-1524, Dec. 1996.
9. M. Kang and W. W.-M. Dai, "General floorplanning with L-shaped, T-shaped and soft blocks based on bounded slicing grid structure," in Proc. ASP-DAC'97, 1997, pp. 265-270.
10. J. Dufour, R. McBride, P. Zhang, and C.-K. Cheng, "A building block placement tool," in Proc. ASP-DAC'97, 1997, pp. 271-276.
11. H. Murata, K. Fujiyoshi, and M. Kaneko, "VLSI/PCB placement with obstacles based on sequence-pair," in Proc. 1997 Int. Symp. Physical Design, Apr. 1997, pp. 26-31.
12. H. Murata, K. Fujiyoshi, and M. Kaneko, "VLSI/PCB placement with obstacles based on sequence-pair," IEEE Trans. Computer-Aided Design, vol. 17, pp. 60-68, Jan. 1998.
13. S. Nakatake, M. Furuya, and Y Kajitani, "Module placement on BSG-structure with preplaced modules and rectilinear modules," in Proc. ASP-DAC'98, 1998, pp. 571-576.
14. J. Xu, P.-N. Guo, and C.-K. Cheng, "Rectilinear block placement using sequence-pair," in Proc Int. Symp. Physical Design, 1998, pp. 173-178.
15. M. Z.-W. Kang and W. W.-M. Dai, "Topology constrained rectilinear block packing," in Proc/J. Symp. Physical Design, 1998, pp. 179-186.
16. K. Fujiyoshi and H. Murata, "A method to pack L-shaped and rectangular modules using sequence-pair," in Proc. 11-th Workshop Circuits and Systems in Karuizawa, Apr. 1998, pp. 113-118. (in Japanese).
17. S. Nakatake, K. Fujiyoshi, H. Murata, and Y. Kajitani, "Module packing based on the BSG-structure and 1C layout applications," IEEE Trans. Computer-Aided Design, vol. 17, pp. 519-530, June 1998.
18. M. Z. Kang and W. W.-M. Dai, "Arbitrary rectilinear block packing based on sequence pair," in Proc. ICCAD'98, 1998, pp. 259-266.
19. K. Sakanushi, S. Nakatake, and Y. Kajitani, "The multi-BSG: Stochastic approach to an optimum packing of convex-rectilinear blocks," in Proc. ICCAD'98, 1998, pp. 267-274.
20. K. Fujiyoshi and H. Murata, "A method to pack L-shaped and rectangular modules using sequence-pair" (in Japanese), IEICE Trans. Fundamentals, to be published.