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Volumn 4, Issue , 2004, Pages
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Power efficient architecture for (3,6)-regular low-density parity-check code decoder
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Author keywords
[No Author keywords available]
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Indexed keywords
BIT ERROR RATE;
CODES (SYMBOLS);
COMPUTATIONAL COMPLEXITY;
COMPUTER ARCHITECTURE;
GRAPH THEORY;
MATRIX ALGEBRA;
TABLE LOOKUP;
THROUGHPUT;
VLSI CIRCUITS;
DECODERS;
MEMORY BUFFERS;
PARITY-CHECK CODES;
POWER DISSIPATION;
DECODING;
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EID: 4344611586
PISSN: 02714310
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (13)
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References (7)
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