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Volumn 4, Issue , 2004, Pages

Power efficient architecture for (3,6)-regular low-density parity-check code decoder

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; CODES (SYMBOLS); COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; GRAPH THEORY; MATRIX ALGEBRA; TABLE LOOKUP; THROUGHPUT; VLSI CIRCUITS;

EID: 4344611586     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (13)

References (7)
  • 3
    • 0036504121 scopus 로고    scopus 로고
    • A 690mW 1-Gb/s 1024-b rate-1/2 low density parity-check code decoder
    • Andrew J. Blanksby and Chris J. Howland, "A 690mW 1-Gb/s 1024-b rate-1/2 low density parity-check code decoder," IEEE Journal of Solid-State Circuits, vol. 37, no. 3, pp. 404-412, 2002.
    • (2002) IEEE Journal of Solid-state Circuits , vol.37 , Issue.3 , pp. 404-412
    • Blanksby, A.J.1    Howland, C.J.2
  • 4
    • 0035294983 scopus 로고    scopus 로고
    • VLSI architecture for iterative decoders in magnetic recording channels
    • March
    • Engling Yeo, Payam Pakzad, Borivoje Nikolic, and Venkat Anantharam, "VLSI architecture for iterative decoders in magnetic recording channels," IEEE Transactions of Magnetics, vol. 37, no. 2, pp. 748-755, March 2001.
    • (2001) IEEE Transactions of Magnetics , vol.37 , Issue.2 , pp. 748-755
    • Yeo, E.1    Pakzad, P.2    Nikolic, B.3    Anantharam, V.4
  • 7
    • 0036954180 scopus 로고    scopus 로고
    • Low-power VLSI decoder architectures for LDPC codes
    • August
    • Mohammad M. Mansour and Naresh R. Shanbhag, "Low-power VLSI decoder architectures for LDPC codes," in ISLPED'02, August 2002, pp. 284-289.
    • (2002) ISLPED'02 , pp. 284-289
    • Mansour, M.M.1    Shanbhag, N.R.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.