Antenna avoidance in layer assignment

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 25, Issue 4, 2006, Pages 734-738

  Wu, Di ^a,b   Hu, Jiang ^c   Mahapatra, Rabi N ^a  

^a TEXAS A AND M UNIVERSITY   (United States)

^b CADENCE DESIGN SYSTEMS   (United States)

^c Department of Electrical and Computer Engineering   (United States)

Author keywords

Antenna effect; Interconnect; Layer assignment (LA); Physical design; Very large scale integration (VLSI)

Indexed keywords

ALGORITHMS; BENCHMARKING; NETWORKS (CIRCUITS); ROUTERS; VLSI CIRCUITS;

ANTENNA EFFECTS; INTERCONNECTS; LAYER ASSIGNMENT (LA); PHYSICAL DESIGN; VERY LARGE SCALE INTEGRATION (VLSI);

ANTENNAS;

EID: 33645683500     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2006.870061     Document Type: Conference Paper

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