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Volumn 3203, Issue , 2004, Pages 975-979

Automated method to generate bitstream intellectual property cores for virtex FPGAs

Author keywords

[No Author keywords available]

Indexed keywords

BINARY SEQUENCES; INTELLECTUAL PROPERTY; INTELLECTUAL PROPERTY CORE;

EID: 84947928278     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-30117-2_110     Document Type: Conference Paper
Times cited : (23)

References (10)
  • 1
    • 0005468712 scopus 로고    scopus 로고
    • VSI Alliance
    • VSIA: VSI Alliance Architecture Document. VSI Alliance, Online http://www.-vsi.org/resources/techdocs/vsi-or.pdf (1997)
    • (1997) VSI Alliance Architecture Document
  • 3
    • 14844331872 scopus 로고    scopus 로고
    • An open platform for development of network processing modules in reprogrammable hardware
    • Santa Clara, CA, WB– 19
    • Lockwood, J.W.: An open platform for development of network processing modules in reprogrammable hardware. In: IEC DesignCon’01, Santa Clara, CA (2001) WB– 19
    • (2001) IEC DesignCon’01
    • Lockwood, J.W.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.