Process-driven variability analysis of single and multiple voltage-frequency island latency-constrained systems

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 27, Issue 5, 2008, Pages 893-904

  Marculescu, Diana ^a,b   Garg, Siddharth ^a,b  

^a IEEE

^b CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

Design variability; Performance analysis; Voltage frequency islands

Indexed keywords

COMPUTER SOFTWARE; EMBEDDED SYSTEMS; PROBLEM SOLVING; RADIO SYSTEMS; VOLTAGE CONTROL;

DESIGN VARIABILITY; PERFORMANCE ANALYSIS; VOLTAGE-FREQUENCY ISLANDS;

ELECTRIC NETWORK TOPOLOGY;

EID: 42649086793     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2008.917969     Document Type: Article

References (30)

1. X. Li, J. Le, P. Gopalakrishnan, and L. T. Pileggi, "Asymptotic probability extraction for non-normal distributions of circuit performance," in Proc. IEEE/ACM ICCAD, San Jose, CA, Nov. 2004, pp. 2-9.
2. M. Orshansky and A. Bandyopadhyay, "Fast statistical timing analysis handling arbitrary delay correlations," in Proc. ACM/IEEE DAC, San Diego, CA, Jun. 2004, pp. 337-342.
3. H. Chang and S. S. Sapatnekar, "Statistical timing analysis considering spatial correlations using a single PERT-like traversal," in Proc. IEEE/ACM ICCAD, San Jose, CA, Nov. 2003, pp. 621-625.
4. I. A. Ferzli and F. N. Najm, "Statistical estimation of leakage-induced power grid voltage drop considering within-die process variations," in Proc. ACM/IEEE DAC, Anaheim, CA, Jun. 2003, pp. 856-859.
5. D. Marculescu and S. Garg, "System-level process-driven variability analysis for single and multiple voltage-frequency island systems," in Proc. IEEE/ACM ICCAD, San Jose, CA, Nov. 2006, pp. 541-546.
6. K. Niyogi and D. Marculescu, "Speed and voltage selection for GALS systems based on voltage/frequency islands," in Proc. ACM/IEEE ASPDAC, Shanghai, China, Jan. 2005, pp. 292-297.
7. H. Wu, I.-M. Liu, M. D. F. Wong, and Y. Wang, "Post-placement voltage island generation under performance requirement," in Proc. IEEE/ACM ICCAD, San Jose, CA, Nov. 2005, pp. 309-316.
8. J. Hu, Y. Shin, N. Dhanwada, and R. Marculescu, "Architecting voltage islands in core-based system-on-a-chip designs," in Proc. ACM/IEEE ISLPED, Newport Beach, CA, Aug. 2004, pp. 180-185.
9. A. W. Shogan, "Bounding distributions for a stochastic PERT network," Networks, vol. 7, no. 4, pp. 359-381, 1977.
10. B. Dodin, Bounding the project completion time distribution in PERT networks," Oper. Res., vol. 33, no. 4, pp. 862-881, Jul./Aug. 1985.
11. W. Kleinöder, "Stochastic analysis of parallel programs for hierarchical multiprocessor systems," Ph.D. dissertation, Univ. Erlangen, Nürnberg, Germany, 1982.
12. M. Colajanni, F. Lo Presti, and S. Tucci, "A hierarchical approach for bounding the completion time distribution of stochastic task graphs," Perform. Eval., vol. 41, no. 1, pp. 1-22, May 2000.
13. J. Y. Brunel, W. M. Kruijtzer, P. Lieverse, and K. A. Vissers, "YAPI: Application modeling for signal processing systems," in Proc. ACM/IEEE DAC, Los Angeles, CA, Jun. 2000, pp. 402-405.
14. IBM Blue Logic Cu-08 voltage islands. [Online]. Available: http://www.ibm.com/chips/products/asics/products/v island.html
15. L. S. Nielson, C. Niessen, J. Sparso, and K. Van Berkel, "Low-power operation using self timed circuits and adaptive scaling of the supply voltage," IEEE Trans. Very large Scale Integr. (VLSI) Syst., vol. 2, no. 4, pp. 391-397, Dec. 1994.
16. J. Muttersbach, T. Villiger, and W. Fichtner, "Practical design of globally asynchronous locally synchronous systems," in Proc. Int Symp. ASYNC, Apr. 2000, pp. 52-59.
17. T. Chelcea and S. M. Nowick, "A low-latency FIFO for mixed-clock systems," in Proc. IEEE Comput. Soc. WVLSI, Apr. 2000, pp. 119-126.
18. A. Dasdan, "Rate analysis of embedded systems," Ph.D. dissertation, Univ. Illinois, Urbana-Champaign, Urbana, IL, 1998.
19. K. A. Bowman, S. G. Duvall, and J. D. Meindl, "Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration," IEEE J. Solid-State Circuits, vol. 37, no. 2, pp. 183-190, Feb. 2002.
20. E. Humenay, D. Tarjan, and K. Skadron, "Impact of process variations on multicore performance symmetry," in Proc. IEEE/ACM DATE. Nice, France, Apr. 2007, pp. 1-6.
21. S. Malik, M. Martonosi, et al.,"Static timing analysis of embedded software, " in Proc. ACM/IEEE DAC, Anaheim, CA, Jun. 1997, pp. 147-152.
22. P. Friedberg, Y. Cao, J. Cain, R. Wang, J. Rabaey, and C. Spanos, "Modeling within-die spatial correlation effects for process-design co-optimization," in Proc. IEEE Int. Symp. Quality Electron. Des., San Jose, CA, Mar. 2005, pp. 516-521.
23. D. Stoyan, Comparison Methods for Queues and Other Stochastic Models. New York: Wiley, 1983.
24. R. E. Barlow and F. Proshan, Statistical Theory of Reliability and Life Testing. New York: Hold, 1975.
25. F. Lo Presti, M. Colajanni, and S. Tucci, "Stochastic bounds on execution times of parallel computations," in Proc. IEEE 2nd Int. Workshop Modeling, Anal., Simul. Comput. Telecommun. Syst., Durham, NC, Feb. 1994, pp. 421-422.
26. A. Devgan and C. Kashyap, "Block based statistical timing analysis with uncertainty," in Proc. IEEE/ACM ICCAD. San Jose, CA, Nov. 2003, pp. 607-614.
27. S. Garg, S. Tata, and R. Arunachalam, "Static transition probability analysis under uncertainty," in Proc. IEEE ICCD, San Jose, CA, Oct. 2004, pp. 380-386.
28. Interconnect-Centric Design for Advanced SoCs and NoCs, J. Nurmi, H. Tenhunen, J. Isoaho, and A. Jantsch, Eds. Norwell, MA: Kluwer, Apr. 2004.
29. U. Ogras and R. Marculescu, "Analytical router modeling for networks-on-chip performance analysis," in Proc. IEEE/ACM DATE, Nice, France, Apr. 2007, pp. 1-6.
30. S. Nassif, "Design for variability in DSM technologies," in Proc. IEEE ISQED, Mar. 2000, pp. 451-454.