Paving the way to a full chip gate level double patterning application

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 6730, Issue , 2007, Pages

  Haffner, Henning ^a   Meiring, Jason ^a   Baum, Zachary ^a   Halle, Scott ^a  

^a IBM RESEARCH   (United States)

Author keywords

Across chip linewidth variation (ACLV); Across device linewidth variation (ADLV); Critical dimension (CD); Decomposition; Double exposure (DE); Double patterning (DP); Printing assist feature (PrAF); Resolution enhancement technique (RET)

Indexed keywords

ACROSS CHIP LINEWIDTH VARIATION (ACLV); ACROSS DEVICE LINEWIDTH VARIATION (ADLV); CRITICAL DIMENSION (CD); DOUBLE EXPOSURE (DE); DOUBLE PATTERNING (DP); PRINTING ASSIST FEATURE (PRAF); RESOLUTION ENHANCEMENT TECHNIQUE (RET);

COMPUTER SIMULATION; DECOMPOSITION; LINEWIDTH; LITHOGRAPHY; PRINTED CIRCUIT DESIGN;

CHIP SCALE PACKAGES;

EID: 42149098956     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.746116     Document Type: Conference Paper

References (8)

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