RF and logic performance improvement of In0.7Ga0.3 As/InAs/In0.7Ga0.3As composite-channel HEMT using gate-sinking technology

IEEE Electron Device Letters

Volumn 29, Issue 4, 2008, Pages 290-293

  Kuo, Chien I ^a   Hsu, Heng Tung ^b   Chang, Edward Yi ^a   Chang, Chia Yuan ^a   Miyamoto, Yasuyuki ^c   Datta, Suman ^d   Radosavljevic, Marko ^d   Huang, Guo Wei ^e   Lee, Ching Ting ^f  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b YUAN ZE UNIVERSITY   (Taiwan)

^c TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

^d INTEL CORPORATION   (United States)

^e NATIONAL NANO DEVICE LABORATORIES   (Taiwan)

^f NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

Author keywords

High electron mobility transistors (HEMTs); InAs; InGaAs; Platinum (Pt) buried gate

Indexed keywords

CAPACITANCE; GATES (TRANSISTOR); INDIUM ARSENIDE; PLATINUM; SEMICONDUCTING INDIUM GALLIUM ARSENIDE; SEMICONDUCTOR DEVICE MANUFACTURE;

GATE-SINKING TECHNOLOGY; PLATINUM BURIED GATE;

HIGH ELECTRON MOBILITY TRANSISTORS;

EID: 41749106677     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2008.917933     Document Type: Article

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