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Volumn , Issue , 2006, Pages 247-252

Fast emulation of permanent faults in VLSI systems

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CURRENTS; ELECTRIC FAULT LOCATION; EXPERIMENTS; FUZZY LOGIC; INJECTION (OIL WELLS); RANDOM ACCESS STORAGE;

EID: 41549099336     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2006.311221     Document Type: Conference Paper
Times cited : (5)

References (15)
  • 4
    • 0242468176 scopus 로고    scopus 로고
    • Using Run-Time Reconfiguration for Fault Injection Applications
    • L. Antoni, et al, "Using Run-Time Reconfiguration for Fault Injection Applications," IEEE Trans. on Instrumentation and Measurement, vol. 52, no. 5, pp. 1468-1473, 2003.
    • (2003) IEEE Trans. on Instrumentation and Measurement , vol.52 , Issue.5 , pp. 1468-1473
    • Antoni, L.1
  • 5
    • 0344362756 scopus 로고    scopus 로고
    • Fault Representativeness,
    • DBench Project, IST-2000-25425
    • P. Gil, et al., "Fault Representativeness,". Deliverable ETIE2, DBench Project, IST-2000-25425, 2002.
    • (2002) Deliverable ETIE2
    • Gil, P.1
  • 6
    • 46249103121 scopus 로고    scopus 로고
    • A. Parreira, J. P. Teixeira and M. Santos A Novel Approach to FPGA-Based Hardware Fault Modelling and Simulation, IEEE Int. Workshop on Design & Diagnostics of Electronic Circuits and Systems, 2003, pp. 17-24.
    • A. Parreira, J. P. Teixeira and M. Santos "A Novel Approach to FPGA-Based Hardware Fault Modelling and Simulation," IEEE Int. Workshop on Design & Diagnostics of Electronic Circuits and Systems, 2003, pp. 17-24.
  • 7
    • 24944439931 scopus 로고    scopus 로고
    • Fast Run-Time Reconfiguration for SEU Injection
    • th European Dependable Computing Conference
    • th European Dependable Computing Conference, LNCS, vol. 3463. 2005, pp. 230-245.
    • (2005) LNCS , vol.3463 , pp. 230-245
    • de Andrés, D.1
  • 10
    • 0003839291 scopus 로고    scopus 로고
    • Validación de sistemas tolerantes a fallos mediante inyección de fallos en modelos VHDL,
    • Ph.D. dissertation, Univ. Politécnica de Valencia, Spain, in Spanish
    • D. Gil, "Validación de sistemas tolerantes a fallos mediante inyección de fallos en modelos VHDL," Ph.D. dissertation, Univ. Politécnica de Valencia, Spain, 1999, in Spanish.
    • (1999)
    • Gil, D.1
  • 11
    • 33845582725 scopus 로고    scopus 로고
    • Run-Time Reconfiguration for Emulating Transient Faults in VLSI Systems
    • to be published
    • D. de Andrés, et al., "Run-Time Reconfiguration for Emulating Transient Faults in VLSI Systems," Int. Conf. on Dependable Systems and Networks, 2006, to be published.
    • (2006) Int. Conf. on Dependable Systems and Networks
    • de Andrés, D.1
  • 12
    • 46249083992 scopus 로고    scopus 로고
    • Virtex 2.5 V Field Programmable Gate Arrays: Functional Description, Xilinx Corp, DS003-2, v2.8.1. 2002.
    • "Virtex 2.5 V Field Programmable Gate Arrays: Functional Description," Xilinx Corp, DS003-2, v2.8.1. 2002.
  • 14
    • 0036534998 scopus 로고    scopus 로고
    • A prototype of a VHDL-based fault injection tool: Description and application
    • J. C. Baraza, et al., "A prototype of a VHDL-based fault injection tool: description and application," Journal of Systems Architecture, vol. 47, no. 10, pp. 847-867, 2002.
    • (2002) Journal of Systems Architecture , vol.47 , Issue.10 , pp. 847-867
    • Baraza, J.C.1
  • 15
    • 46249116091 scopus 로고    scopus 로고
    • 8051 IP Core, Oregano Systems, version 1.4, 2004
    • "8051 IP Core," Oregano Systems, version 1.4, 2004.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.