Techniques and algorithms for fault grading of FPGA interconnect test configurations

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 23, Issue 2, 2004, Pages 261-272

  Tahoori, Mehdi Baradaran ^a   Mitra, Subhasish ^b  

^a Stanford University   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Fault model; Fault simulation; Field programmable gate array (FPGA); Test

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER SIMULATION; FIELD PROGRAMMABLE GATE ARRAYS; LOGIC CIRCUITS;

CONFIGURABLE LOGIC BLOCKS; FAULT GRADING; FAULT SIMULATION; TEST PATTERNS;

COMPUTER AIDED LOGIC DESIGN;

EID: 1242308413     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2003.822112     Document Type: Article

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