An analog CMOS high-speed continuous-time FIR filter

European Solid-State Circuits Conference

Volumn , Issue , 2000, Pages 288-291

  Burlingame, Efram ^a   Spencer, Richard ^a  

^a University of California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG CMOS; BIT WEIGHT; CMOS PROCESSS; CONTINUOUS-TIME; SAMPLING RATES;

CMOS INTEGRATED CIRCUITS; CONTINUOUS TIME SYSTEMS;

FIR FILTERS;

EID: 33746910541     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. P.K.D. Pai, A.D. Brewster and A.A. Abidi, "Analog front-end architectures for high-speed PRML magnetic read channels," IEEE Trans. on Mag., vol. 31, No. 2, March 1995, pp 1103-1108
2. P.M. Aziz and J.L. Sonntag, "Equalizer architecture tradeoffs for magnetic recording channels," IEEE Trans. on Mag., vol. 33, no. 5, Sept. 1997, pp 2728-2730
3. Xiaodong Wang and Richard R. Spencer, "A low power 170MHz discrete-time analog FIR filter," IEEE J. of Solid-State Circuits, Vol. 33, No. 3, March, 1998, pp 417-426
4. Alini et. al., "A 200 MSample/s trellis-coded PRML read/write channel with analog adaptive equalizer and digital servo," IEEE J. of Solid State Circuits, Vol.32, No. 11, Nov, 1997, pp 1824-1838