Threshold voltage in Tunnel FETs: Physical definition, extraction, scaling and impact on IC design

ESSDERC 2007 - Proceedings of the 37th European Solid-State Device Research Conference

Volumn 2007, Issue , 2007, Pages 299-302

  Boucart, Kathy ^a   Ionescu, Adrian M ^a  

^a EPFL   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

DRAIN CURRENT; GATE DIELECTRICS; INTEGRATED CIRCUIT LAYOUT; THRESHOLD VOLTAGE; TRANSCONDUCTANCE;

DRAIN VOLTAGE; GATE LENGTH SCALING; GATE VOLTAGE;

FIELD EFFECT TRANSISTORS;

EID: 39549105378     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.2007.4430937     Document Type: Conference Paper

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