Performance evaluation and optimization of full adders with single-electron technology

Canadian Conference on Electrical and Computer Engineering

Volumn , Issue , 2006, Pages 2136-2139

  Mao, Yanjie ^a   Chen, Chunhong ^a  

^a UNIVERSITY OF WINDSOR   (Canada)

Author keywords

Delay; Full adder; Reliability; SET

Indexed keywords

ELECTRONS; FAULT TOLERANCE; OPTIMIZATION; PARAMETER ESTIMATION;

CORRECT LOGIC OPERATION; RANDOM BACKGROUND CHARGES (RBC);

THRESHOLD LOGIC;

EID: 39049123388     PISSN: 08407789     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CCECE.2006.277366     Document Type: Conference Paper

References (12)

1. M. H. Sulieman and V. Beiu, "On Single-Electron Technology Full Adders," IEEE Transactions on Nanotechnology, vol. 4, pp317-320, no. 6, 2005.
2. C. Lageweg, "Binary Addition Based on Single Electron Tunneling," Proceedings of 2004 IEEE Conference on Nanotechnology, pp327-330, 2004
3. C. Wasshuber, "SIMON - A Simulator for Single-Electron Tunnel Devices and Circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16, pp937-944, no. 9, 1997.
4. K. Yano, T. Ishii, T. Hashimoto, T. Kobayashi, F. Murai, and K. Seki, "Room-temperature Single-electron memory," IEEE Trans. Electron Devices, vol. 41, no. 9, pp. 1628-1638, Sep. 1994.
5. Y. Pashkin, Y. Nakamura, and J. Tsai, "Room -temperature Al single-electron transistor made by electron beam lithography," Appl.Phys. Lett., vol. 76, pp. 2256-2258, May 2000.
6. K. Uchida, J. Koga, R. Ohba, and A. Toriumi, "Room-temperature operation of multifunctional single-electron transistor logic," in IEDM Tech.Dig., Dec. 2000, pp. 863-865.
7. J. Koga, R. Ohba, K. Uchida, and A. Toriumi, "Silicon single-electron memory and logic devices for room temperature operation," in IEDM Tech. Dig., Dec. 2001, pp. 711-714.
8. T. Kim, D. Choo, J. Shim, and S. Kang, "Single-electron transistors operating at room temperature, fabricated utilizing nanocrystals created by focused-ion beam," Appl. Phys. Lett., vol. 80, pp. 2168-2170, Mar. 2002.
9. Y. Tan, T. Kamiya, Z. Durrani, and H. Ahmed, "Room temperature nanocrystalline silicon single-electron transistor," J. Appl. Phys., vol.94, pp. 633-637, Jul. 2003.
10. K. Uchida, J. Koga, R. Ohba, and A. Toriumi, "Programmable singleelectron transistor logic for future low-power intelligent LSI: Proposal and room-temperature operation," IEEE Trans. Electron Devices, vol.50, no. 7, pp. 1623-1630, Jul. 2003.
11. Y. Onu and Y. Takahashi, "Single-Electron Pass-Transistor Logic and its Application to a Binary Adder" Symposium on VLSI Circuits Digest of Technical Papers, 2001
12. C. Lageweg "Binary Addition Based on Single Electron Tunneling" IEEE Conf on Nanotechnology,pp321-330, 2004,