A heterogeneous array of off-chip interconnects for optimum mechanical and electrical performance

Journal of Electronic Packaging

Volumn 129, Issue 4, 2007, Pages 460-468

  Kacker, Karan ^a   Sokol, Thomas ^a   Yun, Wansuk ^b   Swaminathan, Madhavan ^b   Sitaraman, Suresh K ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DIELECTRIC MATERIALS; ELECTRIC PROPERTIES; ELECTROPLATING; FINITE ELEMENT METHOD; MICROPROCESSOR CHIPS; SEMICONDUCTOR MATERIALS; THERMAL EXPANSION;

OFF CHIP INTERCONNECTS; ORTHOGONAL DIRECTIONS; SEMICONDUCTOR INDUSTRY;

INTERCONNECTION NETWORKS;

EID: 38749094088     PISSN: 10437398     EISSN: 15289044     Source Type: Journal    
DOI: 10.1115/1.2804096     Document Type: Article

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