Assembly and reliability assessment of lithography-based wafer-level compliant chip-to-substrate interconnects

Proceedings - Electronic Components and Technology Conference

Volumn 1, Issue , 2005, Pages 545-550

  Kacker, Karan ^a   Lo, George ^a   Sitaraman, Suresh K ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MECHANICAL LOADING; SEQUENTIAL LITHOGRAPHY; SOLDER ATTACHMENT; UNDERFILLS;

ASSEMBLY; LITHOGRAPHY; MICROPROCESSOR CHIPS; SILICON WAFERS; SOLDERING ALLOYS;

OPTICAL INTERCONNECTS;

EID: 24644488936     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

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