Using multi-threshold threshold gates in RTD-based logic design: A case study

Microelectronics Journal

Volumn 39, Issue 2, 2008, Pages 241-247

  Pettenghi, Hector ^a   Avedillo, María J ^a,b   Quintana, José M ^a,b  

^a INSTITUTO DE MICROELECTRÓNICA DE SEVILLA   (Spain)

^b UNIVERSITY OF SEVILLE   (Spain)

Author keywords

MOBILE; Multi threshold threshold gate; Nanopipelining; Resonant tunneling diodes

Indexed keywords

COMPUTATIONAL METHODS; DIODE LOGIC CIRCUITS; ELECTRIC POWER UTILIZATION; LOGIC DESIGN; RESONANT TUNNELING;

BOOLEAN GATES; BUILDING BLOCKS; GATE LEVELS; THRESHOLD GATES;

GATES (TRANSISTOR);

EID: 38549119410     PISSN: 00262692     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mejo.2007.05.015     Document Type: Article

References (11)

1. Mazumder P., Kulkarni S., Bhattacharya M., Sun J.P., and Haddad G.I. Digital circuit applications of resonant tunneling devices. Proc. IEEE 86 4 (1998) 664-686
2. Chen K.J., Maezawa K., and Yamamoto M. InP-based high performance monostable-bistable transition logic elements (MOBILEs) using integrated multiple-input resonant-tunneling devices. IEEE Electron. Device Lett. 17 3 (1996) 127-129
3. Maezawa K., and Mizutani T. A new resonant tunneling logic-gate employing monostable-bistable transition. Jpn. J. Appl. Phys. Lett. 37 (1993) 142-144
4. Pacha C., et al. Threshold logic circuit design of parallel adders using resonant tunnelling devices. IEEE Trans. VLSI Syst. 8 5 (2000) 558-572
5. Muroga S. Threshold Logic and its Applications (1971), Wiley, New York
6. Haring D.R. Multi-threshold threshold elements. IEEE Trans. Electron. Comput. EC-15 1 (1966) 45-65
7. Avedillo M.J., Quintana J.M., Pettenghi H., Kelly P.M., and Thompson C.J. Multi-threshold threshold logic circuit design using resonant tunneling devices. Electron. Lett. 39 (2003) 1502-1504
8. Avedillo M.J., Quintana J.M., and Pettenghi H. Increased logic functionality of clocked series-connected RTDs. IEEE Trans. Nanotechnol. 5 5 (2006) 606-611
9. Pettenghi H., Avedillo M.J., and Quintana J.M. New circuit topology for logic gates based on RTDs. Proc. IEEE Conf. Nanotechnol. (2005) 437-440
10. Chen K.J., Waho T., Maezawa K., and Yamamoto M. An Exclusive-OR logic circuit based on controlled quenching of series-connected negative differential resistance devices. IEEE Electron. Device Lett. 17 6 (1996) 309-311
11. W. Prost, et al., EU IST Report LOCOM No. 28 844 December 2000.