A 3.125-Gb/s clock and data recovery circuit for the 10-Gbase-LX4 ethernet

IEEE Journal of Solid-State Circuits

Volumn 39, Issue 8, 2004, Pages 1356-1360

  Yang, Rong Jyi ^a   Chen, Shang Ping ^a   Liu, Shen Iuan ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

Clock and data recovery (CDR); Frequency detector; Quadricorrelator

Indexed keywords

BANDWIDTH; DATA COMMUNICATION SYSTEMS; DIGITAL CIRCUITS; ELECTRIC POTENTIAL; INTERNET; OPTICAL COMMUNICATION; OPTICAL FIBERS; OSCILLATORS (ELECTRONIC); SIGNAL RECEIVERS; SPECTRUM ANALYSIS; TRANSMITTERS; VARIABLE FREQUENCY OSCILLATORS;

CLOCK AND DATA RECOVERY (CDR); FREQUENCY DETECTORS; OFF-CHIP CAPACITORS; QUADRICORRELATORS; STATE TRANSITIONS;

CLOCKS;

EID: 3843105786     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2004.831809     Document Type: Article

References (10)

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