A shifted-averaging VCO with precise multiphase outputs and low jitter operation

European Solid-State Circuits Conference

Volumn , Issue , 2003, Pages 647-650

  Chang, Hsiang Hui ^a   Chen, Shang Ping ^a   Liu, Shen Iuan ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVE DEVICES; LOW JITTERS; MULTIPHASE-OUTPUT; PHASE ERROR; STATIC PHASE ERRORS;

ERRORS; VARIABLE FREQUENCY OSCILLATORS;

JITTER;

EID: 3843078936     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2003.1257218     Document Type: Conference Paper

References (6)

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2. L. Wu. and W. C. B. Jr., "A low-jitter skew-calibrated multi-phase clock generator for time-interleaved applications", International Symposium on Solid-State Circuits Conference, pp. 396-399, Feb. 2001.
3. H. H. Chang, C. H. Sun and S: I. Liu, " A low-jitter and precise multiphase delay-locked loop using shifted averaging VCDL. " IEEE International Solid-State Circuits Conference, pp. 434-435 and 505, Feb. 2003.
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6. W. S. T. Yan and H. C. Luong, " A 900MHz CMOS low-phase-noise voltage-controlled ring oscillator" IEEE Transactions on circuits and systems II, vol. 48, pp. 216-221, Feb. 2001.