Bit rate and protocol independent clock and data recovery

Electronics Letters

Volumn 36, Issue 9, 2000, Pages 824-825

  Stilling, B ^a  

^a SIEMENS AG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; ELECTRIC NETWORK SYNTHESIS; NETWORK PROTOCOLS; OPTOELECTRONIC DEVICES; PHASE LOCKED LOOPS; VARIABLE FREQUENCY OSCILLATORS;

CLOCK AND DATA RECOVERY CIRCUIT; FREQUENCY DETECTORS; MULTIPLE OCTAVES; OPTOELECTRONIC REGENERATORS;

NETWORKS (CIRCUITS);

EID: 0033731393     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20000603     Document Type: Article

References (4)

1. AFONSO, J.A., QUITERIO, A.J., and ARANTES, D.S.: 'A phase-locked loop with digital frequency comparator for timing signal recovery'. National Telecom. Conf. Rec., 1979, Paper 14.4
2. MESSERSCHMITT, D.G.: 'Frequency detectors for PLL acquisition in timing and carrier recovery', IEEE Trans., 1979, COM-27, pp. 1288-1295
3. POTTBÄCKER, A., LANGMANN, U., and SCHREIBER, H.: 'A Si bipolar phase and frequency detector IC for clock extraction up to 8 Gb/s', IEEE J. Solid-State Circuits, 1992, SC-27, pp. 1747-1751
4. HOGGE, C.R.: 'A self correcting clock recovery circuit', IEEE J. Lightwave Technol., 1985, LT-3, (6), pp. 1312-1314