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Volumn 2002-January, Issue , 2002, Pages 29-40

Model-based exploration of the design space for heterogeneous systems on chip

Author keywords

Cost function; Digital signal processing; Field programmable gate arrays; Power dissipation; Process design; Silicon; Space exploration; System on a chip; Technological innovation; Throughput

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; COST FUNCTIONS; DESIGN; DIGITAL SIGNAL PROCESSING; ELECTRIC LOSSES; ENERGY DISSIPATION; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); MICROPROCESSOR CHIPS; PROCESS DESIGN; PRODUCT DESIGN; PROGRAM PROCESSORS; PROGRAMMABLE LOGIC CONTROLLERS; SIGNAL PROCESSING; SILICON; SPACE RESEARCH; STRUCTURAL DESIGN; SYSTEM-ON-CHIP; THROUGHPUT;

EID: 84882411795     PISSN: 10636862     EISSN: None     Source Type: Journal    
DOI: 10.1109/ASAP.2002.1030702     Document Type: Article
Times cited : (24)

References (20)
  • 1
    • 85013969116 scopus 로고    scopus 로고
    • website
    • Altera, website, http://www.altera.com
  • 2
    • 84948763657 scopus 로고    scopus 로고
    • White Paper, June 00
    • Altera, Excalibur Backgrounder, http://www.altera.com/literature/wp/excal-bkgrnd.pdf, White Paper, June 00
    • Excalibur Backgrounder
  • 3
    • 14844355101 scopus 로고    scopus 로고
    • Analyzing heterogeneous system architectures by means of cost functions: A comparative study for basic operations
    • Blume, H.; Feldkämper, H.; Hübert, H.; Noll, T.G.: "Analyzing heterogeneous system architectures by means of cost functions: A comparative study for basic operations", Proc. ESSCIRC 2001, pp. 424-427
    • Proc. Esscirc 2001 , pp. 424-427
    • Blume, H.1    Feldkämper, H.2    Hübert, H.3    Noll, T.G.4
  • 6
    • 0034174025 scopus 로고    scopus 로고
    • The Density Advantage of Configurable Computing
    • April
    • De Hon, A.: "The Density Advantage of Configurable Computing", IEEE Computer, April 2000, pp. 41-49
    • (2000) Ieee Computer , pp. 41-49
    • De Hon, A.1
  • 8
    • 14844364643 scopus 로고    scopus 로고
    • Integrated Circuits for Next Generation Wireless Systems
    • Hausner, J.: "Integrated Circuits for Next Generation Wireless Systems", Proc. ESSCIRC 2001, pp. 26-29
    • Proc. Esscirc 2001 , pp. 26-29
    • Hausner, J.1
  • 10
    • 85013891434 scopus 로고    scopus 로고
    • Karn, P. http://people.qualcomm.com/karn/code/index.html, 1996
    • (1996)
    • Karn, P.1
  • 13
    • 0033724504 scopus 로고    scopus 로고
    • Parallel Viterbi algorithm for a VLIW DSP
    • Khan, S. A.; Saqib, M.; Ahmed, S.: "Parallel Viterbi algorithm for a VLIW DSP", ASSP'2000, pp. 3390-3
    • Assp'2000 , pp. 3390-3393
    • Khan, S.A.1    Saqib, M.2    Ahmed, S.3
  • 16
    • 0029777661 scopus 로고    scopus 로고
    • An Architecture overview of the programmable multimedia processor TM 1000
    • IEEE CS Press
    • Rathnam, S.; Slavenburg, G.: "An Architecture overview of the programmable multimedia processor TM 1000", Proc. Compcon, IEEE CS Press, 1996, pp. 319-326
    • (1996) Proc. Compcon , pp. 319-326
    • Rathnam, S.1    Slavenburg, G.2
  • 17
    • 0035341885 scopus 로고    scopus 로고
    • Reconfigurable Computing for Digital Signal Processing: A Survey
    • Tessier, R.; Burleson, W.: "Reconfigurable Computing for Digital Signal Processing: A Survey", Journal of VLSI Signal Processing 28, 2001, pp. 7-27
    • (2001) Journal Of Vlsi Signal Processing , vol.28 , pp. 7-27
    • Tessier, R.1    Burleson, W.2
  • 20
    • 3042805764 scopus 로고    scopus 로고
    • A flexible Datapath Generator for Physical Oriented Design
    • Weiss, O.; Gansen, M.; Noll, T. G.: "A flexible Datapath Generator for Physical Oriented Design", Proc. ESSCIRC 2001, pp.408-11
    • Proc. Esscirc 2001 , pp. 408-411
    • Weiss, O.1    Gansen, M.2    Noll, T.G.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.