Temporal partitioning and scheduling for reconfigurable computing

Proceedings - IEEE Symposium on FPGAs for Custom Computing Machines, FCCM 1998

Volumn 1998-April, Issue , 1998, Pages 329-330

  Gajjalapurna, K M ^a   Bhatia, D ^a  

^a UNIVERSITY OF CINCINNATI   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; DIRECTED GRAPHS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE; RECONFIGURABLE ARCHITECTURES; SCHEDULING;

CUSTOM COMPUTING MACHINES; DATA DEPENDENCIES; DIRECTED ACYCLIC GRAPHS; HARDWARE RESOURCES; REAL APPLICATIONS; RECONFIGURABLE; RECONFIGURABLE COMPUTING; TEMPORAL PARTITIONING;

RECONFIGURABLE HARDWARE;

EID: 84956869964     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPGA.1998.707939     Document Type: Conference Paper

References (4)

1. Duncan A. Buell, Je-rey M. Arnold, Walter J. Kleinfelde \Splash2, FPGAs in Custom Com-puting Machine, " IEEE Computer Society Press, Los Alamitos, California.
2. M. Vasilko, Djamel Ait-Boudaoud, \Scheduling for dynamically Recon-gurable FPGAs, " Pro-ceedings of International workshop on Logic and Architecture synthesis, IFIP TC10 WG10. 5, Dec 1995.
3. Doug Smith, Dinesh Bhatia, \RACE: Recon-g-urable and Adaptive Computing Environment, " Proceedings of 6th Int. Workshop on Field Pro-grammable Logic and Applications, FPL 96, Ger-many
4. Daniel D. Gajski, Nikil D. Dutt, Allen C-H Wu, Steve Y-L Lin, \High-level synthesis, Introduc-tion to chip and system design, " Kluwer Aca-demic publishers, 1992.