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Volumn 4873 LNCS, Issue , 2007, Pages 133-146

Efficient message management in tiled CMP architectures using a heterogeneous interconnection network

Author keywords

Chip multiprocessor; Energy efficient architectures; Heterogeneus on chip interconnection network; Parallel scientific applications

Indexed keywords

COMPUTER ARCHITECTURE; ELECTRIC POWER UTILIZATION; ENERGY EFFICIENCY; INFORMATION MANAGEMENT; INTERCONNECTION NETWORKS; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS;

EID: 38349028513     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-77220-0_16     Document Type: Conference Paper
Times cited : (5)

References (19)
  • 1
    • 0036505033 scopus 로고    scopus 로고
    • The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs
    • Taylor, M.B., Kim, J., et al.: The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs. IEEE Micro 22(2), 25-35 (2002)
    • (2002) IEEE Micro , vol.22 , Issue.2 , pp. 25-35
    • Taylor, M.B.1    Kim, J.2
  • 2
    • 27544495466 scopus 로고    scopus 로고
    • Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors
    • Zhang, M., Asanovic, K.: Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors. In: Proc. of the 32nd Int'l Symp. on Computer Architecture, pp. 336-345 (2005)
    • (2005) Proc. of the 32nd Int'l Symp. on Computer Architecture , pp. 336-345
    • Zhang, M.1    Asanovic, K.2
  • 6
    • 0036866915 scopus 로고    scopus 로고
    • A power-optimal repeater insertion methodology for global interconnects in nanometer designs
    • Banerjee, K., Mehrotra, A.: A power-optimal repeater insertion methodology for global interconnects in nanometer designs. IEEE Trans. on Electron Devices 49(11), 2001-2007 (2002)
    • (2002) IEEE Trans. on Electron Devices , vol.49 , Issue.11 , pp. 2001-2007
    • Banerjee, K.1    Mehrotra, A.2
  • 9
    • 35248847114 scopus 로고    scopus 로고
    • Flores, A., Aragón, J.L., Acacio, M.E.: Sim-PowerCMP: A Detailed Simulator for Energy Consumption Analysis in Future Embedded CMP Architectures. In: Proc. of the 4th Int'l Symp. on Embedded Computing, pp. 752-757 (2007)
    • Flores, A., Aragón, J.L., Acacio, M.E.: Sim-PowerCMP: A Detailed Simulator for Energy Consumption Analysis in Future Embedded CMP Architectures. In: Proc. of the 4th Int'l Symp. on Embedded Computing, pp. 752-757 (2007)
  • 10
    • 0036470602 scopus 로고    scopus 로고
    • RSIM: Simulating Shared-Memory Multiprocessors with ILP Processors
    • Hughes, C.J., Pai, V.S., et al.: RSIM: Simulating Shared-Memory Multiprocessors with ILP Processors. IEEE Computer 35(2), 40-49 (2002)
    • (2002) IEEE Computer , vol.35 , Issue.2 , pp. 40-49
    • Hughes, C.J.1    Pai, V.S.2
  • 12
    • 34249306904 scopus 로고    scopus 로고
    • HotLeakage: A Temperature-Aware Model of Subthreshold and Gate Leakage for Architects
    • Technical report, University of Virginia
    • Zhang, Y., Parikh, D., et al.: HotLeakage: A Temperature-Aware Model of Subthreshold and Gate Leakage for Architects. Technical report, University of Virginia (2003)
    • (2003)
    • Zhang, Y.1    Parikh, D.2
  • 13
  • 16
    • 31844455497 scopus 로고    scopus 로고
    • Alleviating Thermal Constraints while Maintaining Performance via Silicon-Based On-Chip Optical Interconnects
    • Nelson, N., Briggs, G., et al.: Alleviating Thermal Constraints while Maintaining Performance via Silicon-Based On-Chip Optical Interconnects. In: Workshop on Unique Chips and Systems (2005)
    • (2005) Workshop on Unique Chips and Systems
    • Nelson, N.1    Briggs, G.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.