A high-level compact pattern-dependent delay model for high-speed point-to-point interconnects

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2006, Pages 323-328

  Murgan, Tudor ^a   Momeni, Massoud ^a   Ortiz, Alberto García ^a   Glesner, Manfred ^a  

^a DARMSTADT UNIVERSITY OF TECHNOLOGY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN; ELECTRIC LINES; ELECTRIC POWER SYSTEM INTERCONNECTION; MOBILE TELECOMMUNICATION SYSTEMS; PROGRAMMING THEORY;

APPLIED (CO); CAPACITIVELY COUPLED; COMPUTER-AIDED DESIGN; DELAY MODELING; HIGH SPEEDS; IN ORDER; INTERNATIONAL CONFERENCES; LEVELS OF ABSTRACTION (LOA); POINT-TO-POINT INTERCONNECTS; PROCESS VARIATIONS; SIGNAL DELAYS; SWITCHING PATTERNS; VERY DEEP SUB MICRON (VDSM);

MODAL ANALYSIS;

EID: 37849044597     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2006.320053     Document Type: Conference Paper

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