A 175 mV multiply-accumulate unit using an adaptive supply voltage and body bias (ASB) architecture

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2002, Pages 58-59+444+51

  Miyazaki, Masayuki ^a   Kao, James ^a   Chandrakasan, Anantha P ^a  

^a Massachusetts Institute of Technology Cambridge   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIGITAL TO ANALOG CONVERSION; ELECTRIC POWER UTILIZATION; LEAKAGE CURRENTS; MICROPROCESSOR CHIPS; OSCILLATORS (ELECTRONIC); POWER SUPPLY CIRCUITS; TABLE LOOKUP; THRESHOLD VOLTAGE;

DELAY LOCKED LOOP (DLL) CIRCUITS;

DIGITAL SIGNAL PROCESSING;

EID: 0036114022     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. Embedded power supply for low-power DSP
2. A variable-frequency parallel I/O interface with adaptive power-supply regulation
3. A scalable performance 32b microprocessor
4. 2, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme
5. Automatic adjustment of threshold & supply voltage for minimum power consumption in CMOS digital circuits
6. A 1000 MIPS/W microprocessor using speed-adaptive threshold-voltage CMOS with forward bias