A novel low-power and high-speed SOI SRAM with actively body-bias controlled (ABC) technology for emerging generations

IEEE Transactions on Electron Devices

Volumn 55, Issue 1, 2008, Pages 365-371

  Hirano, Yuuichi ^a   Tsujiuchi, Mikio ^a   Maki, Yukio ^a   Iwamatsu, Toshiaki ^a   Ishii, Yuichiro ^a   Miyanishi, Atsushi ^a   Tsukamoto, Yasumasa ^a   Nii, Koji ^a   Ipposhi, Takashi ^a   Oda, Hidekazu ^a   Maegawa, Shigeto ^a   Inoue, Yasuo ^a  

^a RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

Access time; Body bias; Multicell errors; Neutron; Silicon on insulator (SOI); Soft error rate (SER); Soft errors; Static random access memory (SRAM); System on a chip (SoC); Variation

Indexed keywords

CAPACITANCE; ELECTRIC CURRENTS; ELECTRIC POTENTIAL; ERRORS; SILICON ON INSULATOR TECHNOLOGY; TRANSISTORS;

ACTIVELY BODY-BIAS CONTROLLED TECHNOLOGY; SOFT ERROR RATE; SYSTEM ON A CHIP;

STATIC RANDOM ACCESS STORAGE;

EID: 37749017381     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2007.910566     Document Type: Article

References (13)

1. A. Asenov, "Random dopant induced threshold voltage lowering and fluctuations in sub-0.1 μm MOSFETs: A 3-D 'atomistic' simulation study," IEEE Trans. Electron Devices, vol. 45, no. 12, pp. 2505-2513, Dec. 1998.
2. T. Mizuno, J. Okumtura, and A. Toriumi, "Experimental study of threshold voltage fluctuation due to statistical variation of channel dopant number in MOSFETs," IEEE Trans. Electron Devices, vol. 41, no. 11, pp. 2216-2221, Nov. 1994.
3. J. P. Colinge, "An SOI voltage-controlled bipolar-MOS device," IEEE Trans. Electron Devices, vol. ED-34, no. 4, pp. 845-849, Apr. 1987.
4. F. Assaderaghi, D. Sinitsky, S. A. Parke, J. Bokor, P. K. Ko, and C. Hu, "Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSL" IEEE Trans. Electron Devices, vol. 44, no. 3, pp. 414-422, Mar. 1997.
5. Y. Hirano, S. Maeda, T. Matsumoto, K. Nii, T. Iwamatsu, Y. Yamaguchi, T. Ipposhi, H. Kawashima, S. Maegawa, M. Inuishi, and T. Nishimura, "Bulk-layout-compatible 0.18-μm SOI-CMOS technology using body-tied partial-trench-isolation (PTI)," IEEE Trans. Electron Devices, vol. 48, no. 12, pp. 2816-2822, Dec. 2001.
6. Y. Hirano, T. Matsumoto, S. Maeda, T. Iwamatsu, T. Kunikiyo, K. Nii, K. Yamamoto, Y. Yamaguchi, T. Ipposhi, S. Maegawa, and M. Inuislu, "Impact of 0.10 μm SOI CMOS with body-tied hybrid trench isolation structure to break through the scaling crisis of silicon technology," in IEDM Tech. Dig., 2000, pp. 467-470.
7. Y. Hirano, T. Ipposhi, H. T. Dang, T. Matsumoto, T. Iwamatsu, K. Nii, Y. Tsukamoto, T. Yoshizawa, H. Katou, S. Maegawa, K. Arimoto, M. Inuishi, and Y. Ohji, "Impact of actively body-bias controlled (ABC) SOI SRAM by using direct body contact technology for low-voltage application," in IEDM Tech. Dig., 2003, pp. 35-38.
8. Y. Maki, Y. Hirano, M. Tsujiuchi, T. Iwamatsu, O. Ozawa, T. Ipposhi, and Y. Inoue, "Improvement of device characteristics variation by using a body-bias controlling technology based on a hybrid trench isolated SOI" in Proc. SSDM Tech. Dig., 2006, pp. 360-361.
9. T. Iwamatsu, M. Tsujiuchi, Y. Hirano, T. Ikeda, F. Komatsu, T. Ipposhi, S. Maegawa, and Y. Ohji, "Impact of body bias controlling in partially depleted SOI devices with hybrid trench isolation technology," in Proc. SSDM Tech. Dig., 2005, pp. 886-887.
10. P. E. Dodd, M. R. Shaneyfelt, J. R. Schwank, and G. L. Hash, "Neutron-induced soft errors, latchup, and comparison of SER test methods for SRAM technologies," in IEDM Tech. Dig., 2002, pp. 333-336.
11. J. Maiz, S. Hareland, K. Zhang, and P. Armstrong, "Characterization of multi-bit soft error events in advanced SRAMs," in IEDM Tech. Dig. 2003, pp. 519-522.
12. Y. Hirano, T. Iwamatsu, K. Shiga, K. Nii, K. Sonoda, T. Matsumoto, S. Maeda, Y. Yamaguchi, T. Ipposhi, S. Maegawa, and Y. Inoue, "High soft-error tolerance body-tied SOI technology with partial trench isolation (PTI) for next generation devices," in VLSI Symp. Tech. Dig., 2002, pp. 48-49.
13. Y. Wada, K. Nii, H. Kuriyama, S. Maeda, K. Ueda, and Y. Matsuda, "A 128-kb SRAM with soft error immunity for 0.35 μm SOI-CMOS embedded cell arrays," in Proc. IEEE Int. SOI Conf., 1998, pp. 127-128.