Elimination of single event latchup in 90NM SRAM technologies

IEEE International Reliability Physics Symposium Proceedings

Volumn , Issue , 2006, Pages 721-722

  Puchner, H ^a   Kapre, R ^a   Sharifzadeh, S ^a   Majjiga, J ^a   Chao, R ^a   Radaelli, D ^a   Wong, S ^a  

^a CYPRESS SEMICONDUCTOR   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPREHENSIVE REVIEW; DATASHEET; OPERATING CONDITIONS; SINGLE EVENT LATCHUP;

CMOS INTEGRATED CIRCUITS; ELECTRIC CURRENTS; ELECTRIC NETWORK ANALYSIS; ERROR ANALYSIS; SUBSTRATES;

STATIC RANDOM ACCESS STORAGE;

EID: 34250720522     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RELPHY.2006.251342     Document Type: Conference Paper

References (3)

1. G.Bruguier and J.-M. Palau, "Single particle induced latchup", IEEE Trans. Nucl. Sci., 43(2), pp.522-532, 1996
2. P.Dodd, M.Shaneyfelt, J.Schwank, and G.Hash, "Neutron-Induced Latchup in SRAMs at Ground Level", IRPS 2003, pp.51-55, 2003
3. P.Layton, D.Czajkowski, J.Marshall, H. Antony, and R. Boss, "Single Event Latchup Protection of Integrated Circuits", RADECS 97, pp.327 - 331, 1997