Scaling limits of double-gate and surround-gate Z-RAM cells

IEEE Transactions on Electron Devices

Volumn 54, Issue 9, 2007, Pages 2255-2262

  Butt, Nauman Z ^a   Alam, Muhammad Ashraful ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

Capacitorless; Double gate; Quantum confinement; Scaling; Simulation; Surround gate

Indexed keywords

ELECTRON TUNNELING; GATES (TRANSISTOR); QUANTUM CONFINEMENT; SEMICONDUCTOR DOPING;

SINGLE EVENT UPSETS; SOURCE/DRAIN-TO-BODY JUNCTIONS;

RANDOM ACCESS STORAGE;

EID: 37249049901     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2007.902691     Document Type: Article

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