Latch design techniques for mitigating single event upsets in 65 nm SOI device technology

IEEE Transactions on Nuclear Science

Volumn 54, Issue 6, 2007, Pages 2021-2027

  KleinOsowski, A J ^a   Cannon, Ethan H ^b   Gordon, Michael S ^c   Heidel, David F ^c   Oldiges, Phil ^b   Plettner, Cristina ^c,d   Rodbell, Kenneth P ^c   Rose, Ronald D ^b   Tang, Henry H K ^c  

^a IBM AUSTIN RESEARCH LABORATORY   (United States)

^b IBM   (United States)

^c IBM T J WATSON RESEARCH CENTER   (United States)

^d ICX Technologies   (Germany)

Author keywords

Alpha particle; Modeling; Radiation event; Single event upset (SEU); Soft error

Indexed keywords

ALPHA PARTICLES; COMPUTER HARDWARE; ERROR ANALYSIS; FLIP FLOP CIRCUITS;

RADIATION EVENTS; SINGLE EVENT UPSET (SEU); SOFT ERROR;

SILICON ON INSULATOR TECHNOLOGY;

EID: 37249006354     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2007.909707     Document Type: Conference Paper

References (12)

1. T. Heijmen, P. Roche, G. Gasiot, and K. R. Forbes, "A comparative study on the soft-error rate of flip-flops from 90-nm production libraries," in Proc. IEEE Int. Reliabil. Phys. Symp. (IRPS), Apr. 2006, pp. 204-211.
2. T. Calin, M. Nicolaidis, and R. Velazco, "Upset hardened memory design for submicron CMOS technology," IEEE Trans. Nucl. Sci., vol. 43, no. 6, pp. 2874-2878, Dec. 1996.
3. A. J. Drake, A. KleinOsowski, and A. K. Martin, "A self-correcting soft error tolerant flip-flop," presented at the 12th NASA Symp. VLSI Design, Coeur d'Alene, ID, Oct. 2005.
4. E. H. Cannon, D. D. Reinhardt. M. S. Gordon, and P. S. Makowenskyj, "SRAM SER in 90, 130, and 180 nm bulk and SOI technologies," in Proc. IEEE Int. Reliabil. Phys. Symp. (IRPS), 2004, pp. 300-304.
5. P. Roche and G. Gasiot, "Impacts of front-end and middle-end process modifications on terrestrial soft enor rate," IEEE Trans. Device Mater. Reliabil., vol. 5, no. 3, pp. 382-396, Sep. 2005.
6. E. Leobandung et al., "High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell," in Symp. VLSI Technology Dig. Tech. Papers, 2005, pp. 126-127.
7. "BSIMSOI User's Guide," Univ. of California, Berkeley [Online]. Available: http://www-device.eecs.berkeley.edu/~bsimsoi/
8. "PowerSPICE User's Guide," Available from IBM Corporation, Department 16SA. 1580 Route 2, Hopewell Junction. NY.
9. A. KleinOsowski, P. Oldiges, P. M. Solomon, and R. Q. Williams, "Modeling single-event upsets in 65-nm silicon-on-insulator semiconductor devices," IEEE Trans. Nucl. Sci., vol. 53, no. 6, pp. 3321-3328, Dec. 2006.
10. D. F. Heidel, K. P. Rodbell, P. Oldiges, M. S. Gordon, H. H. Tang, E. Cannon, and C. Plettner, "Single-event-upset critical charge measurements and modeling of 65 nm silicon-on-insulator latches and memory cells," IEEE Trans. Nucl. Sci., vol. 53, no. 6, pp. 3512-3517, Dec. 2006.
11. H. Fukui, M. Hamaguchi, H. Yoshimura, H. Oyamatsu, F. Matsuoka, T. Noguchi, T. Hirao, H. Abe, S. Onoda, T. Yamakawa, T. Wakasa, and T. Kamiya, "Comprehensive study on layout dependence of soft errors in CMOS latch circuits and its scaling trend for 65 nm technology node and beyond," in Symp. VLSI Technology Dig. Tech. Papers, 2005, pp. 222-223.
12. T. Karnik, B. Bloechel, K. Soumyanath, V. De, and S. Borkar, "Scaling trends of cosmic rays induced soft errors in static latches beyond o.1 sum," in Symp. VLSI Circuits (VLSI) Dig., 2001, pp. 61-62.