Comprehensive study on layout dependence of soft errors in CMOS latch circuits and its scaling trend for 65 nm technology node and beyond

Digest of Technical Papers - Symposium on VLSI Technology

Volumn 2005, Issue , 2005, Pages 222-223

  Fukui, H ^a   Hamaguchi, M ^a   Yoshimura, H ^a   Oyamatsu, H ^a   Matsuoka, F ^a   Noguchi, T ^a   Hirao, T ^b   Abe, H ^b   Onoda, S ^b   Yamakawa, T ^b   Wakasa, T ^b   Kamiya, T ^b  

^a TOSHIBA CORPORATION   (Japan)

^b JAPAN ATOMIC ENERGY AGENCY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DIFFUSION; ELECTRIC POTENTIAL; ELECTRIC POWER SYSTEMS; ERROR ANALYSIS; OPTIMIZATION;

CHARGE COLLECTION; CMOS LATCH CIRCUITS; SER DEGRADATION; SOFT-ERROR RATE (SER);

CMOS INTEGRATED CIRCUITS;

EID: 33745138789     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/.2005.1469276     Document Type: Conference Paper

References (4)

1. J. F. Ziegler e. al., IBM J. R&D, vol. 40, p. 3, 1996.
2. T. Karnik et al., VLSI Symp. Circ. Dig. p. 61, 2001.
3. N. Yanagiya et al., IEDM Tech. Dig. p. 57, 2002.
4. JEDEC Test Specification JESD89