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Volumn , Issue , 2007, Pages
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Prediction of the influence of induced stresses in silicon on CMOS performance in a cu-through-Via interconnect technology
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Author keywords
[No Author keywords available]
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Indexed keywords
CMOS INTEGRATED CIRCUITS;
COMPUTER SIMULATION;
COPPER;
FINITE ELEMENT METHOD;
LARGE SCALE SYSTEMS;
MICROPROCESSOR CHIPS;
TRANSISTORS;
CHIP STACKINGS;
INTERCONNECT TECHNOLOGY;
SILICON THICKNESS;
THERMOCOMPRESSION BONDINGS;
SILICON;
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EID: 36349032313
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/ESIME.2007.360030 Document Type: Conference Paper |
Times cited : (14)
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References (14)
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