Prediction of the influence of induced stresses in silicon on CMOS performance in a cu-through-Via interconnect technology

EuroSime 2007: International Conference on Thermal, Mechanical and Multi-Physics Simulation Experiments in Microelectronics and Micro-Systems, 2007

Volumn , Issue , 2007, Pages

  Okoro, Chukwudi ^a,b   Gonzalez, Mario ^a   Vandevelde, Bart ^a   Swinnen, Bart ^a   Eneman, Geert ^a,b   Verheyen, Peter ^a   Beyne, Eric ^a   Vandepitte, Dirk ^b  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; COPPER; FINITE ELEMENT METHOD; LARGE SCALE SYSTEMS; MICROPROCESSOR CHIPS; TRANSISTORS;

CHIP STACKINGS; INTERCONNECT TECHNOLOGY; SILICON THICKNESS; THERMOCOMPRESSION BONDINGS;

SILICON;

EID: 36349032313     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESIME.2007.360030     Document Type: Conference Paper

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