An analog programmable multidimensional radial basis function based classifier

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 54, Issue 10, 2007, Pages 2148-2158

  Peng, Sheng Yu ^a   Hasler, Paul E ^a   Anderson, David V ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Analog classifier; Bump circuit; Floating gate transistor; Gaussian like analog circuit; Radial basis function (RBF); Vector quantizer

Indexed keywords

GATES (TRANSISTOR); MAXIMUM LIKELIHOOD; MICROPROCESSOR CHIPS; PROBABILITY DISTRIBUTIONS; VECTOR QUANTIZATION;

BUMP CIRCUIT; FLOATING-GATE TRANSISTOR;

RADIAL BASIS FUNCTION NETWORKS;

EID: 36348956891     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2007.905642     Document Type: Article

References (20)

1. P. Hasler, P. D. Smith, D. Graham, R. Ellis, and D. V. Anderson, "Analog floating-gate, on-chip auditory sensing system interfaces," IEEE J. Sensors, vol. 5, no. 5, pp. 1027-1034, Oct. 2005.
2. M. Ogawa, K. Ito, and T. Shibata, "A general-purpose vector-quantization processor employing two-dimensional bit-propagating winnertake-all," in Proc. Symp. VLSI Syst., Jun. 13-15, 2002, pp. 244-247.
3. M. Bracco, S. Ridella, and R. Zunino, "Digital implementation of hierarchical vector quantization," IEEE Trans. Neural Netw., vol. 14, no. 5, pp. 1072-1084, Sep. 2003.
4. G. Cauwenberghs and V. Pedron, "A low-power CMOS analog vector quantizer," IEEE J. Solid-State Circuits, vol. 32, no. 8, pp. 1278-1283, Aug. 1997.
5. P. Hasler, P. Smith, C. Duffy, C. Gordon, J. Dugger, and D. Anderson, "A floating-gate vector- quantizer," in Proc. Midwest. Symp. Circuits Syst., Aug. 2002, vol. 1, pp. 196-199.
6. T. Yamasaki and T. Shibata, "Analog soft-pattern-matching classifier using floating-gate MOS technology," IEEE Trans. Neural Netw., vol. 14, no. 5, pp. 1257-1265, Sep. 2003.
7. T. Delbruck, "'Bump' circuits for computing similarity and dissimilarity of analog voltage," in Proc. Int. Neural Network Society, Seattle, WA, 1991.
8. S. S. Watkins and P. M. Chart, "A radial basis function neurocomputer implemented with analog VLSI circuits," in Proc. Int. Joint Conf. Neural Networks, 1992, vol. 2, pp. 607-612.
9. J. Choi, B. J. Sheu, and J. C.-F. Chang, "A Gaussian synapse circuit for analog neural networks," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 2, no. 3, pp. 129-133, Mar. 1994.
10. S.-Y. Lin, R.-J. Huang, and T.-D. Chiueh, "A tunable Gaussian/square function computation circuit for analog neural networks," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 45, no. 3, pp. 441-446, 1998.
11. D. S. Masmoudi, A. T. Dieng, and M. Masmoudi, "A subthreshold mode programmable implementation of the Gaussian function for RBF neural networks applications," in, Proc. 2002 IEEE Int. Symp. Intelligent Control, Vancouver, Cananda, Oct. 2002, pp. 454-459.
12. D. Hsu, M. Figueroa, and C. Diorio, "A silicon primitive for competitive learning," in Proc. Conf. Neural Inf. Processing Syst. Dec. 2000, pp. 713-719.
13. P. Hasler, "Continuous-time feedback in floating-gate MOS circuits," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 48, no. 1, pp. 56-64, Jan. 2001.
14. M. Kucic, A. Low, P. Hasler, and J. Neff, "A programmable continuous-time floating-gate Fourier processor," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 48, no. 1, pp. 90-99, Jan. 2001.
15. A. Bandyopadhyay, G. J. Serrano, and P. Hasler, "Adaptive algorithm using hot-electron injection for programming analog computational memory elements within 0.2% of accuracy over 3.5 decades," IEEE J. Solid-State Circuits, vol. 41, no. 9, pp. 2107-2114, Sep. 2006.
16. P. Hasler and J. Dugger, "Correlation learning rule in floating-gate pFET synapses," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 48, no. 1, pp. 65-73, Jan. 2001.
17. V. Srinivasan, G. J. Serrano, J. Gray, and P. Hasler, "A precision cmos amplifier using floating-gates for offset cancellation," in Proc. CICC'05, Sep. 2005, pp. 734-737.
18. J. Glossner, K. Chirca, M. Schulte, H. Wang, N. Nasimzada, D. Har, S. Wang, A. J. Hoane, G. Nacer, M. Moudgill, and S. Vassiliadis, "Sandblaster low power DSP," in Prec. IEEE Custom Integr. Circuits Conf., Oct. 2004, pp. 575-581.
19. R. Chawla, A. Bandyopadhyay, V. Srinivasan, and P. Hasler, "A 531-nW/MHz, 128 X 32 current-mode programmable analog vector-matrix multiplier with over two decades of linearity," in Prec. IEEE Custom Integr. Circuits Conf., Oct. 2004, pp. 651-654.
20. R. Karakiewicz, R. Genov, A. Abbas, and G. Cauwenberghs, "175 GMACS/mW charge-mode adiabatic mixed-signal array processor," in Proc. Symp. VLSI Syst., Jun. 2006.