Digital Implementation of Hierarchical Vector Quantization

IEEE Transactions on Neural Networks

Volumn 14, Issue 5, 2003, Pages 1072-1084

  Bracco, Massimiliano ^a   Ridella, Sandro ^a   Zunino, Rodolfo ^a  

^a UNIVERSITY OF GENOA   (Italy)

Author keywords

Digital very large scale integration (VLSI); Minimum description length (MDL); Vector quantization (VQ)

Indexed keywords

COMPUTER HARDWARE; COST EFFECTIVENESS; FIELD PROGRAMMABLE GATE ARRAYS; HIERARCHICAL SYSTEMS; REAL TIME SYSTEMS; VECTOR QUANTIZATION;

DIGITAL CIRCUITRY; MINIMUM DESCRIPTION LENGTH (MDL);

VLSI CIRCUITS;

EID: 0242611600     PISSN: 10459227     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNN.2003.816355     Document Type: Article

References (33)

1. IEEE Trans Inform. Theory (Special Issue on Vector Quantization), vol. IT-28, Mar. 1982.
2. A. Gersho and R. M. Gray, Vector Quantization and Signal Compression. Norwell, MA: Kluwer, 1992.
3. T. Kohonen, Self-Organization and Associative Memory, 3rd ed. New York: Springer-Verlag, 1989.
4. T. M. Martinetz, S. G. Berkovich, and K. J. Schulten, '"Neural gas' network for vector quantization and its application to time-series prediction," IEEE Trans. Neural Neworks., vol. 4, pp. 558-569, July 1993.
5. N. Ueda and R. Nakano, "A new competitive learning approach based on an equidistortion principle for designing optimal vector quantizers," Neural Networks, vol. 7, no. 8, pp. 1211-1228, 1994.
6. S. Ridella, S. Rovetta, and R. Zunino, "K-winner machines for pattern classification," IEEE Trans. Neural Networks, vol. 12, pp. 371-385, Mar. 2001.
7. Y. Linde, A. Buzo, and R. M. Gray, "An Algorithm for vector quantizer design," IEEE Trans. Commun., vol. COM-28, pp. 84-95, Jan. 1980.
8. R. Jain, A. Madisetti, and R. L. Baker, "An integrated circuit design for pruned tree-search vector quantization encoding with an off-chip controller," IEEE Trans. Circuits Syst. Video Technol., vol. 2, pp. 147-158, June 1992.
9. K. Tsang and B. W. Y. Wei, "A VLSI architecture for a real-time code book generator and encoder of a vector quantizer," IEEE Trans. VLSI Syst., vol. 2, pp. 360-364, Sept. 1994.
10. W. C. Fang, C. Y. Chang, B. J. Sheu, O. T. C. Chen, and J. C. Curlander, "VLSI systolic binary tree-searched vector quantizer for image compression," IEEE Trans. VLSI Syst., vol. 2, pp. 33-44, Mar. 1994.
11. G. Cauwenberghs and V. Pedroni, "A low-power CMOS analog vector quantizer," IEEE J. Solid-State Circuits, vol. 32, pp. 1278-1283, Aug. 1997.
12. T. Serrano-Gotarredona and B. Linares-Barranco, "A real-time clustering microchip neural engine," IEEE Trans. VLSI Syst., vol. 4, pp. 195-209, June 1996.
13. S. Rovetta and R. Zunino, "Efficient training of neural gas vector quantizers with analog circuit implementation," IEEE Trans. Circuits Syst. II, vol. 46, pp. 688-698, June 1999.
14. A. Lipman and W. Yang, "VLSI hardware for example-based learning," IEEE Trans. VLSI Syst., vol. 5, pp. 320-328, Sept. 1997.
15. T. Nozawa, M. Konda, M. Fujibayashi, M. Imai, K. Kotani, S. Sugawa, and T. Ohmi, "A parallel vector-quantization processor eliminating redundant calculations for real-time motion picture compression," IEEE J. Solid-State Circuits, vol. 35, pp. 1744-1751, Nov. 2000.
16. J. Rissanen, Stochastic Complexity in Statistical Inquiry. Singapore: World Scientific, 1989.
17. K. Dezhgosha, M. M. Jamali, and S. C. Kwatra, "A VLSI architecture for real-time image coding using a vector quantization based algorithm," IEEE Trans. Signal Processing, vol. 40, pp. 181-189, Jan. 1992.
18. W. C. Fang, B. J. Sheu, O. T. C. Chen, and J. Choi, "A VLSI neural processor for image data compression using self-organization networks," IEEE Trans. Neural Networks, vol. 3, pp. 506-518, May 1992.
19. J. Rissanen, "A universal prior for integers and estimation by minimum description length," Ann. Statist., vol. 11, no. 2, pp. 416-431, 1983.
20. J.-N. Liaw and R. L. Kashyap, "A new sequential classifier using information criterion window," Pattern Recognition, vol. 27, no. 10, pp. 1423-1438, 1994.
21. Y. Liu, "Unbiased estimate of generalization error and model selection in neural network," Neural Networks, vol. 8, pp. 215-219, 1995.
22. H. Akaike, "A new look at the statistical model identification," IEEE Trans. Automat. Contr., vol. AC-19, pp. 716-722, Dec. 1974.
23. D. B. Fogel, "An information criterion for optimal neural network selection," IEEE Trans. Neural Networks, vol. 2, pp. 490-497, Sept. 1991.
24. J. Rissanen, "Stochastic complexity and modeling," Ann. Statist., vol. 14, no. 3, pp. 1080-1100, 1986.
25. B. Widrow, I. Kollár, and M.-C. Liu, "Statistical theory of quantization," IEEE Trans. Instrum. Meas., vol. 45, pp. 353-361, Apr. 1996.
26. D. L. Neuhoff, "On the asymptotic distribution of the errors in vector quantization," IEEE Trans. Inform. Theory, vol. 42, pp. 461-468, Mar. 1996.
27. N. Nasrabadi and R. King, "Image coding using vector quantization: A review," IEEE Trans. Commun., pp. 957-971, Aug. 1988.
28. R. Dony and S. Haykin, "Neural network approaches to image compression," Proc. IEEE, vol. 83, pp. 288-303, Feb. 1995.
29. C. Amerijck, M. Verleysen, P. Thissen, and J. D. Legat, "Image compression by self-organizing Kohonen map," IEEE Trans. Neural Networks, vol. 9, pp. 503-507, May 1998.
30. S. Ridella, S. Rovetta, and R. Zunino, "IAVQ: Interval-arithmetics vector quantization for image compression," IEEE Trans. Circuits Syst. II, vol. 47, pp. 1378-1390, Dec. 2000.
31. S. Rovetta and R. Zunino, "Vector quantization for license-plate location and image coding," IEEE Trans. Ind. Electron., vol. 47, pp. 159-167, Feb. 2000.
32. S. Ridella and R. Zunino, "Empirical measure of multiclass generalization performance: The K-winner machine case," IEEE Trans. Neural Networks, vol. 12, pp. 1525-1529, Nov. 2001.
33. D. Anguita, S. Ridella, F. Rivieccio, and R. Zunino, "Hyperparameter design criteria for support vector classifiers," Neurocomputing, 2003, to be published.