Analog Soft-Pattern-Matching Classifier Using Floating-Gate MOS Technology

IEEE Transactions on Neural Networks

Volumn 14, Issue 5, 2003, Pages 1257-1265

  Yamasaki, Toshihiko ^a   Shibata, Tadashi ^a  

^a UNIVERSITY OF TOKYO   (Japan)

Author keywords

Analog very large scale integration (VLSI); Floating gate metal oxide semiconductor (MOS); Low power; Pattern classification; Template matching; Vector quantization

Indexed keywords

ALGORITHMS; EDGE DETECTION; IMAGE CODING; PATTERN MATCHING; VECTOR QUANTIZATION; VLSI CIRCUITS;

HADWRITTEN PATTERNS; SOFT-PATTERN MATCHING;

MOS DEVICES;

EID: 0242526854     PISSN: 10459227     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNN.2003.816031     Document Type: Article

References (27)

1. M. Yagi, M. Adachi, and T. Shibata, "A hardware-friendly soft-computing algorithm for image recognition," in Proc. 10th European Signal Processing Conf. (EUSIPCO 2000), Tampere, Finland, Sept. 4-8, 2000, pp. 729-732.
2. M. Adachi and T. Shibata, "Image representation algorithm featuring human perception of similarity for hardware recognition systems," in Proc. Int. Conf. Artificial Intell., vol. I, H. R. Arabnia, Ed., Las Vegas, NV, June 25-28, 2001, pp. 229-234.
3. M. Yagi and T. Shibata, "A human-perception-like image recognition system based on PPED vector representation with multi resolution concept," in Proc. 2002 IEEE Int. Conf. Acoustics, Speech, Signal Processing, vol. I, May 13-17, 2002, pp. 1041-1048.
4. M. Yagi, T. Shibata, and K. Takada, "Human-perception-like image recognition system based on the associative processor architecture," in Proc. XI European Signal Processing Conf., vol. 2, Toulouse, France, Sept. 3-6, 2002, pp. 729-732.
5. M. Yagi and T. Shibata, An Image Representation Algorithm Compatible to Neural-Associative-Processor-Based Hardware Recognition Systems, to be published.
6. A. Gersho and R. M. Gray, Vector Quantization and Signal Compression. Boston, MA: Kluwers, 1992.
7. K. Kobayashi, M. Kinoshita, M. Takeuchi, H. Onodera, and K. Tamaru, "A memory-based parallel processor for vector quantization," in Proc. 22nd European Solid-State Circuits Conf., Sep. 1996, pp. 184-187.
8. A. Nakada, T. Shibata, M. Konda, T. Morimoto, and T. Ohmi, "A fully parallel vector quantization processor for real-time motion picture compression," IEEE J. Solid-State Circuits, vol. 34, pp. 822-830, June 1999.
9. M. Ogawa, K. Ito, and T. Shibata, "A general-purpose vector-quantization processor employing two-dimensional bit-propagating winner-take-all," in Digest Technical Papers 2002 Symp. VLSI Circuits, Honolulu, HI, June 13-15, 2002, pp. 244-247.
10. G. T. Tuttle, S. Fallahi, and A. A. Abidi, "An 8b CMOS vector A/D converter," in ISSCC Tech. Digest, vol. 36, 1993, pp. 38-39.
11. B. Liu, C. Y. Chen, and J. Y. Tsao, "A modular current-mode classifier circuit for template matching application," IEEE Trans. Circuits Syst. II, vol. 47, pp. 145-151, Feb. 2000.
12. G. Cauwenberghs and V. Pedroni, "A charge-based CMOS parallel analog vector quantizer," in Advances in Neural Information Processing Systems 7, G. Tesauro, D. S. Touretzky, and T. K. Leen, Eds. Cambridge, MA: MIT Press, 1995, pp. 779-786.
13. M. Konda, T. Shibata, and T. Ohmi, "Neuron-MOS correlator based on manhattan distance computation for event recognition hardware," in Proc. 1996 IEEE Int. Symp. Circuit Syst., vol. 4, Atlanta, GA, May 1996, pp. 217-220.
14. J. Anderson, J. C. Platt, and D. B. Kirk, "An analog VLSI chip for radial basis functions," in Advances in Neural Information Processing Systems, vol. 5, S. J. Hanson, J. D. Cowan, and C. L. Giles, Eds., San Maetro, CA, 1993, pp. 765-772.
15. L. Theogarajan and L. A. Akers, "A multi-dimensional ana-log gaussian radial basis circuit," presented at the IEEE Int. Symp. Circuits Syst., Atlanta, GA, 1996.
16. _, "A scalable low voltage analog gaussian radial basis circuit," IEEE Trans. Circuits Syst. II, vol. 44, pp. 977-977, Nov. 1997.
17. E. Sackinger, B. E. Boser, J. Bromley, Y. LeCun, and L. D. Jackel, "Application of the ANNA neural network chip to high-speed character recognition," IEEE Trans. Neural Network, vol. 3, pp. 498-505, May 1992.
18. T. Yamasaki and T. Shibata, "An analog similarity evaluation circuit featuring variable functional forms," in Proc. 2001 IEEE Int. Symp. Circuits Syst., Sydney, Australia, May. 6-9, 2001, pp. III-561-564.
19. T. Yamasaki. K. Yamamoto. and T. Shibata, "Analog pattern classifier with flexible matching circuitry based on principal-axis-projection vector representation," in Proc. 27th European Solid-State Circuits Conf., F. Dielacher and H. Grunbacher, Eds., Villach, Austria, Sept. 18-20, 2001, pp. 212-215.
20. T. Yamasaki and T. Shibata, "Analog soft-pattern-matching classifier using floating-gate MOS technology," in Advances in Neural Inform. Processing Syst. 14, Proc. 14th Conf. Neural Information Processing Systems: Natural and Synthetic (NIPS*2001), T. G. Dietterich, S. Becker, and Z. Ghahramani, Eds., Vancouver, BC, Canada, Dec. 2001, pp. 1131-1138.
21. T. Shitaba and T. Ohmi, "A functional MOS transistor featuring gate-level weighted sum and threshold operations." IEEE Trans. Electron Devices, vol. 39, no. 6, pp. 1444-1455, 1992.
22. K. Ito, M. Ogawa, and T. Shibata, "A high-performance time-domain winner-take-all circuit employing OR-tree architecture," in Extended Abstracts, 2001 Int. Conf. Solid-State Devices Materials, Tokyo, Japan, Sept. 26-28, 2001, pp. 94-95.
23. _, "A high-performance ramp-voltage-scan winner-take-all circuit in an open loop architecture," Japanese J. Appl. Phys., pt. Part 1, vol. 41, no. 4B, pp. 2301-2305, Apr. 2002.
24. M. Yagi and T. Shibata, "An associative-processor-based mixed signal system for robust image recognition," in Proc. 2002 IEEE Int. Symp. Circuits Syst., May 26-29, 2002, pp. V-137-V-140.
25. T. Yamasaki, A. Suzuki, D. Kobayashi, and T. Shibata, "A fast self-convergent flash-memory programming scheme for MV and analog data storage," in Proc. 2001 IEEE Int. Symp. Circuits Syst., Sydney, Australia, May 6-9, 2001, pp. IV-930-933.
26. T. Shibata, T. Nakai, N. M. Yu, Y. Yamashita, M. Konda, and T. Ohmi, "Advances in neuron-MOS applications," in Digest Tech. Papers, 1996 IEEE Int. Solid-State-Circuit Conf., San Francisco, CA, February 1996, pp. 304-305.
27. T. Sakai and T. Matsumoto, "Fast parallel spatial filters using floating-gate transistor array" (in Japanese), in Proc. 1996 IEICE General Conf., vol. C-2, Mar. 1996, p. 196.