A general-purpose vector-quantization processor employing two-dimensional bit-propagating winner-take-all

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2002, Pages 244-247

  Ogawa, Makoto ^a   Ito, Kiyoto ^a   Shibata, Tadashi ^a  

^a UNIVERSITY OF TOKYO   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; TWO DIMENSIONAL; VECTOR QUANTIZATION;

VECTOR QUANTIZATION PROCESSOR CHIPS; WINNER TAKE ALL CIRCUITS;

MICROPROCESSOR CHIPS;

EID: 0242611623     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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