High performance combinatorial algorithm design on the Cell Broadband Engine processor

Parallel Computing

Volumn 33, Issue 10-11, 2007, Pages 720-740

  Bader, David A ^a   Agarwal, Virat ^a   Madduri, Kamesh ^a   Kang, Seunghwa ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Cell Broadband Engine processor; Combinatorial algorithms; Graph algorithms; List ranking; Multicore; Novel architectures; Parallel algorithms; Performance; zlib

Indexed keywords

COMPUTATIONAL METHODS; MICROPROCESSOR CHIPS; PARALLEL ALGORITHMS; PARALLEL PROCESSING SYSTEMS; PROBLEM SOLVING; PROGRAM PROCESSORS;

CELL BROADBAND ENGINE PROCESSORS; COMBINATORIAL ALGORITHMS; GRAPH ALGORITHMS; LIST RANKING;

COMBINATORIAL MATHEMATICS;

EID: 35748930871     PISSN: 01678191     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.parco.2007.09.005     Document Type: Article

References (26)

1. D.A. Bader, G. Cong. A fast, parallel spanning tree algorithm for symmetric multiprocessors (SMPs), in: Proceedings of the International Parallel and Distributed Processing Symposium (IPDPS 2004), Santa Fe, NM, April 2004.
2. D.A. Bader, G. Cong, Fast shared-memory algorithms for computing the minimum spanning forest of sparse graphs, in: Proceedings of the International Parallel and Distributed Processing Symposium (IPDPS 2004), Santa Fe, NM, April 2004.
3. D.A. Bader, G. Cong, J. Feo, On the architectural requirements for efficient execution of graph algorithms, in: Proceedings of the 34th International Conference on Parallel Processing (ICPP), Oslo, Norway, June 2005.
4. Bader D.A., Sreshta S., and Weisse-Bernstein N. Evaluating arithmetic expressions using tree contraction: a fast and scalable parallel implementation for symmetric multiprocessors (SMPs). In: Sahni S., Prasanna V.K., and Shukla U. (Eds). Proceedings of the Ninth International Conference on High Performance Computing (HiPC 2002), Bangalore, India. Lecture Notes in Computer Science vol. 2552 (2002), Springer-Verlag 63-75
5. D.A. Brokenshire, Maximizing the power of the Cell Broadband Engine Processor: 25 tips to optimal application performance, IBM developerWorks technical article, 2006.
6. T. Chen, R. Raghavan, J. Dale, E. Iwata, Cell Broadband Engine Architecture and its first implementation, IBM developerWorks technical article, 2005.
7. Cole R., and Vishkin U. Faster optimal prefix sums and list ranking. Information and Computation 81 3 (1989) 344-352
8. D.E. Culler, R.M. Karp, D.A. Patterson, A. Sahay, K.E. Schauser, E. Santos, R. Subramonian, T. von Eicken, LogP: towards a realistic model of parallel computation, in: Proceedings of the Fourth Symposium Principles and Practice of Parallel Programming, ACM SIGPLAN, May 1993, pp. 1-12.
9. P. Deutsch, J.-L. Gailly, zlib compressed data format specification version 3.3, Internet RFCs, 1996.
10. B. Flachs et al., A streaming processor unit for a Cell processor, in: Proceedings of the International Solid State Circuits Conference, vol. 1, San Fransisco, CA, USA, February 2005, pp. 134-135.
11. Helman D.R., and JáJá J. Designing practical efficient algorithms for symmetric multiprocessors. Algorithm Engineering and Experimentation (ALENEX'99), Baltimore, MD. Lecture Notes in Computer Science vol. 1619 (1999), Springer-Verlag 37-56
12. Helman D.R., and JáJá J. Prefix computations on symmetric multiprocessors. Journal of Parallel and Distributed Computing 61 2 (2001) 265-278
13. Huffman D.A. A method for the construction of minimum-redundancy codes. Proceedings of the IRE 40 9 (1952) 1098-1101
14. C. Jacobi, H.-J. Oh, K.D. Tran, S.R. Cottier, B.W. Michael, H. Nishikawa, Y. Totsuka, T. Namatame, N. Yano, The vector floating-point unit in a synergistic processor element of a Cell processor, in: Proceedings of the 17th IEEE Symposium on Computer Arithmetic, Washington, DC, USA, 2005, IEEE (ARITH'05) Computer Society, pp. 59-67.
15. JáJá J. An Introduction to Parallel Algorithms (1992), Addison-Wesley Publishing Company, New York
16. Joshi S.M., Dubey P.K., and Kaplan M.A. A new parallel algorithm for CRC generation. IEEE International Conference on Communications 3 (2000) 1764-1768
17. Kahle J.A., Day M.N., Hofstee H.P., Johns C.R., Maeurer T.R., and Shippy D. Introduction to the Cell multiprocessor. IBM Journal of Research Development 49 4/5 (2005) 589-604
18. Kistler M., Perrone M., and Petrini F. Cell multiprocessor communication network: built for speed. IEEE Micro 26 3 (2006) 10-23
19. B. Lin, Altivec solutions to sequential problems: calculating CRC with scalable congruent equivalent compression, Freescale application note AN2926, January 2006.
20. K. Margaritis, Vectorization of algorithm Adler32 using altivec. freevec.org whitepaper, 2005.
21. D. Pham et al. The design and implementation of a first-generation Cell processor, in: Proceedings of the International Solid State Circuits Conference, vol. 1, San Fransisco, CA, USA, February 2005, pp. 184-185.
22. Ramachandran V. A general-purpose shared-memory model for parallel computation. In: Heath M.T., Ranade A., and Schreiber R.S. (Eds). Algorithms for Parallel Processing vol. 105 (1999), Springer-Verlag, New York 1-18
23. Reid-Miller M. List ranking and list scan on the Cray C-90. Journal of Computer and System Sciences 53 3 (1996) 344-356
24. Valiant L.G. A bridging model for parallel computation. Communications of the ACM 33 8 (1990) 103-111
25. S. Williams, J. Shalf, L. Oliker, S. Kamil, P. Husbands, K. Yelick, The potential of the Cell processor for scientific computing, in: Proceedings of the Third Conference on Computing Frontiers CF'06, 2006, ACM Press, New York, NY, USA, pp. 9-20.
26. Ziv J., and Lempel A. A universal algorithm for sequential data compression. IEEE Transactions on Information Theory 23 3 (1977) 337-343