New parallel algorithm for CRC generation

IEEE International Conference on Communications

Volumn 3, Issue , 2000, Pages 1764-1768

  Joshi, Sanjay M ^a   Dubey, Pradeep K ^a   Kaplan, Marc A ^a  

^a UNIVERSITY OF MARYLAND BALTIMORE COUNTY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; COMPUTER SOFTWARE; ERROR DETECTION; MICROPROCESSOR CHIPS; PARALLEL ALGORITHMS; REDUNDANCY; TABLE LOOKUP;

BIT WISE SERIAL ALGORITHMS; CYCLIC REDUNDANCY CHECK (CRC); ETHERNET;

COMPUTER NETWORKS;

EID: 0033682613     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (20)