A cycle accurate power estimation tool

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2006, Issue , 2006, Pages 867-870

  Chaudhry, Rajat ^a   Stasiak, Daniel ^a   Posluszny, Stephen ^a   Dhong, Sang ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ENERGY UTILIZATION; LOGIC DESIGN; MATHEMATICAL MODELS; POWER INTEGRATED CIRCUITS; PROGRAM PROCESSORS; SWITCHING; TRANSISTORS;

CLOCK ACTIVITY; MACRO POWER MODELS; POWER ESTIMATION TOOLS; POWER MANAGEMENT LOGIC;

VLSI CIRCUITS;

EID: 33748593622     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1118299.1118496     Document Type: Conference Paper

References (4)

1. Subodh Gupta and Farid N Najim, Power Modeling for High Level Power Estimation, IEEE transaction on VLSI, vol 8. No 1, Feb 2000.
2. Brooks et al., Power-aware microarchitecture: design and modeling challenges for next-generation microprocessors, Micro, IEEE, Volume: 20, Issue: 6, Nov.-Dec. 2000 Pages: 26-44
3. Neely, J.S et al., CPAM: a common power analysis methodology for high-performance VLSI design, Electrical Performance of Electronic Packaging, 2000, IEEE Conference on., 23-25 Oct. 2000
4. E Behnen et al, Ontology of The First Generation CELL Microprocessor, Submitted to DAC 2005.