Evolution of fault-tolerant and noise-robust digital designs

IEE Proceedings: Computers and Digital Techniques

Volumn 151, Issue 4, 2004, Pages 287-294

  Hartmann, M ^a   Haddow, P C ^a  

^a NORWEGIAN UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Norway)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; CMOS INTEGRATED CIRCUITS; COMBINATORIAL CIRCUITS; COMPUTER HARDWARE; COMPUTER SIMULATION; FAULT TOLERANT COMPUTER SYSTEMS; GENETIC ALGORITHMS; INTEGRATED CIRCUIT LAYOUT; MULTIPLYING CIRCUITS; NAND CIRCUITS; SPURIOUS SIGNAL NOISE;

ADDER CIRCUITS; DIGITAL CIRCUIT DESIGN; EVOLVABLE HARDWARE; MULTIPLIER CIRCUITS;

DIGITAL INTEGRATED CIRCUITS;

EID: 3543105492     PISSN: 13502387     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1049/ip-cdt:20040014     Document Type: Article

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