Impact of process variation on 65nm across-chip linewidth variation

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 6156, Issue , 2006, Pages

  Hong, Le ^a   Brist, Travis ^a   LaCour, Pat ^a   Sturtevant, John ^a   Niehoff, Martin ^b   Niedermaier, Philipp ^c  

^a MENTOR GRAPHICS CORPORATION   (United States)

^b Mentor Graphics Corporation   (Germany)

^c INFINEON TECHNOLOGIES AG   (Germany)

Author keywords

ACLV; CD variation; Gate; OPC; Verification

Indexed keywords

ACLV; CD VARIATION; GRID-BASED SIMULATION; OPC; VERIFICATION;

COMPUTER SIMULATION; CORRELATION METHODS; GATES (TRANSISTOR); PHOTOLITHOGRAPHY; PROCESS CONTROL;

CHIP SCALE PACKAGES;

EID: 33745802199     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.660541     Document Type: Conference Paper

References (3)

1. Toublan, O., Lucas, K., Entradas, J., Borjon, A., Patterson, K., Miramond, C., Trouiller, Y., Belledent., J, "Verification Requirements for 45nm and 65nm Optical Proximity Correct." Interface Symposium, (2005).
2. Sturtevant, J., Word, J., LaCour, P., Park, J., Smith, D., "Assessing the impact of real world manufacturing lithography variations on post-OPC CD control", Proc. SPIE 5756, 240, (2005).
3. Maurer, Word, J, Schulze, S., Shang, S., " MEEF-based mask inspection" Proc. SPIE 5567, 98 (2004).