Leakage Power Analysis and Comparison of Deep Submicron Logic Gates

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 3254, Issue , 2004, Pages 198-207

  Merrett, Geoff ^a   Al Hashimi, Bashir M ^a  

^a UNIVERSITY OF SOUTHAMPTON   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK TOPOLOGY; LOGIC CIRCUITS; LOGIC GATES; LOW POWER ELECTRONICS; RECONFIGURABLE HARDWARE; TOPOLOGY;

BERKELEY PREDICTIVE TECHNOLOGY MODELS; CMOS DIGITAL CIRCUITS; COMPLEMENTARY PASS-TRANSISTOR LOGIC; DEEP SUB-MICRON TECHNOLOGY; DOUBLE PASS TRANSISTOR LOGIC; FUNDAMENTAL BUILDING BLOCKS; LEAKAGE POWER ANALYSIS; VOLTAGE SWITCH LOGIC;

COMPUTER CIRCUITS;

EID: 35048890243     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-30205-6_22     Document Type: Article

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