Enhanced thermal efficiency in phase-change memory cell by double GST thermally confined structure

IEEE Electron Device Letters

Volumn 28, Issue 10, 2007, Pages 871-873

  Chao, Der Sheng ^a,b   Chen, Yi Chen ^a   Chen, Fred ^a   Chen, Ming Jung ^a   Yen, Philip H ^a   Lee, Chain Ming ^a   Chen, Wei Su ^a   Lien, Chenhsin ^b   Kao, Ming Jer ^a   Tsai, Ming Jinn ^a  

^a INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

^b NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

Chalcogenide material; Ge2Sb2Te5 (GST); Phase change memory (PCM); Programming current; Thermal nonuniformity

Indexed keywords

CHALCOGENIDES; FABRICATION; PULSE WIDTH MODULATION; SEMICONDUCTOR DEVICE STRUCTURES; TEMPERATURE; THERMAL EFFECTS;

PHASE-CHANGE MEMORY CELL; THERMAL EFFICIENCY;

PHASE CHANGE MEMORY;

EID: 34948898551     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2007.906084     Document Type: Article

References (12)

1. Y. H. Ha, J. H. Yi, H. Horii, J. H. Park, S. H. Joo, S. O. Park, U.-I. Chung, and J. T. Moon, "An edge contact type cell for phase change RAM featuring very low power consumption," in VLSI Symp. Tech. Dig., 2003, pp. 175-176.
2. F. Pellizzer, A. Pirovano, F. Ottogalli, M. Magistretti, M. Scaravaggi, P. Zuliani, M. Tosi, A. Benvenuti, P. Besana, S. Cadeo, T. Marangon, R. Morandi, R. Piva, A. Spandre, R. Zonca, A. Modelli, E. Varesi, T. Lowrey, A. Lacaita, G. Casagrande, P. Cappelletti, and R. Bez, "Novel μtrench phase-change memory cell for embedded and stand-alone non-volatile memory applications," in VLSI Symp. Tech. Dig., 2004, pp. 18-19.
3. S. J. Ahn, Y. N. Hwang, Y. J. Song, S. H. Lee, S. Y. Lee, J. H. Park, C. W. Jeong, K. C. Ryoo, J. M. Shin, J. H. Park, Y. Fai, J. H. Oh, G. H. Koh, G. T. Jeong, S. H. Joo, S. H. Choi, Y. H. Son, J. C. Shin, Y. T. Kim, H. S. Jeong, and K. Kim, "Highly reliable 50 nm contact cell technology for 256 Mb PRAM," in VLSI Symp. Tech. Dig., 2005, pp. 98-99.
4. H. Horii, J. H. Yi, J. H. Park, Y. H. Ha, I. G. Baek, S. O. Park, Y. N. Hwang, S. H. Lee, Y. T. Kim, K. H. Lee, U.-I. Chung, and J. T. Moon, "A novel cell technology using N-doped GeSbTe films for phase change RAM," in VLSI Symp. Tech. Dig., 2003, pp. 177-178.
5. N. Matsuzaki, K. Kurotsuchi, Y. Matsui, O. Tonomura, N. Yamamoto, Y. Fujisaki, N. Kitai, R. Takemura, K. Osada, S. Hanzawa, H. Moriya, T. Iwasaki, T. Kawahara, N. Takaura, M. Terao, M. Matsuoka, and M. Moniwa, "Oxygen-doped GeSbTe phase-change memory cells featuring 1.5-V/100-μA standard 0.13-μm CMOS operations," in IEDM Tech. Dig., 2005, pp. 738-741.
6. L. P. Shi, T. C. Chong, J. M. Li, H. X. Yang, and J. Q. Mou, "Thermal analysis of nonvolatile and non rotation phase change memory cell," in Proc. Mater. Res. Soc. Symp., 2004, vol. 803, pp. HH1.8.1-HH1.8.6.
7. S. L. Cho, J.H. Yi, Y. H. Ha, B. J. Kuh, C.M. Lee, J.H. Park, S. D. Nam, H. Horii, B. O. Cho, K. C. Ryoo, S. O. Park, H. S. Kim, U.-I. Chung, J. T. Moon, and B. I. Ryu, "Highly scalable on-axis confined cell structure for high density PRAM beyond 256 Mb," in VLSI Symp. Tech. Dig., 2005, pp. 96-97.
8. S. M. Sadeghipour, L. Pileggi, and M. Asheghi, "Phase change random access memory, thermal analysis," in Proc. ITHEM, 2006, pp. 660-665.
9. A. Pirovano, A. L. Lacaita, A. Benvenuti, F. Pellizzer, S. Hudgens, and R. Bez, "Scaling analysis of phase-change memory technology," in IEDM Tech. Dig., 2003, pp. 29.6.1-29.6.4.
10. 5 in optical and electrical memory devices," J. Appl. Phys., vol. 95, no. 2, pp. 504-511, Jan. 2004.
11. C. D. Wright, M. Armand, M. M. Aziz, R. A. Cobley, S. Senkader, and W. Yu, "Simulation studies on electrical, thermal, and phase-change behavior of GeSbTe based memory devices," in Proc. EPSOS, 2003.
12. Y.-T. Kim, K.-H. Lee, W.-Y. Chung, T.-K. Kim, Y.-K. Park, and J.-T. Kong, "Study on cell characteristics of PRAM using the phase-change simulation," in Proc. SISPAD, 2003, pp. 211-214.